# US 12,400,700 B2 · Memory device provided with dram memory circuits arranged in such a way as to minimize the size of a memory block allowing management of the row-hammering

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- Number: US 12,400,700 B2
- Document ID: US12400700B2
- Status: Granted
- Kind: B2
- Application number: 18/277,961
- Filed: 2022-02-11
- Published: 2024-04-25
- Granted: 2025-08-26
- Earliest claimed: 2021-02-22
- Assignees: Upmem
- Applicants: Upmem
- Inventors: Fabrice Devaux
- Web page: https://patentgrep.com/patent/US12400700B2

## CPC

- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 7/02: with means for avoiding parasitic signals
- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 11/40622: {Partial refresh of memory arrays}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The invention relates to a memory device comprising: —DRAM memory circuits (100), the total capacity of which is divided into a first part (102) and a second part (103) larger than the first part (102); —a control circuit configured to access the memory circuits, the control circuit comprising: —a first block (201) configured to execute a first algorithm (201A) intended to protect the first part (102) from a row-hammering effect; —a second block (202) configured to execute a second algorithm (202A) intended to protect the second part (103) from a row-hammering effect that may occur, the second algorithm (202A) using a main table stored in the first part (102).

## Claims

### Claim 1

A memory device (10) comprising:
memory circuits (100), these circuits comprise memories of “DRAM” type, the total capacity of which is divided into a first part (102), called the “directly protected part”, and a second part (103), called the “indirectly protected part”, larger than the first part (102);
a control circuit (200) configured to access the memory circuits, the control circuit comprises:
a first block (201) configured to execute a first algorithm (201A) intended to protect the first part (102) from a row-hammering effect;
a second block (202) configured to execute a second algorithm (202A) intended to protect the second part (103) from the row-hammering effect that may occur, the second algorithm (202A) using a main table stored in the first part (102).

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein the control circuit comprises a functional block (300) configured to execute computing functions and programs in the second part (103).

### Claim 3 (depends on 1)

The device according to claim 1, wherein the first part (102) and the second part (103) are arranged so that a row-hammering effect imposed by one row of either the first part (102) or the second part (103) is not felt by the other of the first part (102) or second part (103).

### Claim 4 (depends on 3)

The device according to claim 3, wherein the first part (102) and the second part (103) are configured according to one of the following configurations:
the first part (102) and the second part (103) are disjoint so as not to share DRAM memory circuits;
the first part (102) and the second part (103) each comprise banks of DRAM memory circuits specific to them;
the first part (102) and the second part (103), within the same bank of DRAM memory circuits, each comprise one or more sub-banks that are specific to them, said sub-banks are then arranged so that a row-hammering effect exerted by a row of a sub-bank of the first part (102) is not felt by a sub-bank of the second part (103) and vice versa;
the first part (102) and the second part (103) have in common a DRAM memory circuit bank, called a common bank, said common bank comprising unused memory rows and separating a section of the common bank, associated with the first part (102), from another section of the common bank, associated with the second part (103), the number of unused memory rows being chosen so that no row-hammering effect occurs between each of the two sections of the common bank.

### Claim 5 (depends on 1)

The device according to claim 1, wherein the first part (102) and the second part (103) are capable of exerting a row-hammering effect on one another, and wherein the first algorithm (201A) and the second algorithm (202A) are configured to prevent the row-hammering effect of the first part (102) on the second part (103) and vice versa.

### Claim 6 (depends on 1)

The device according to claim 1, wherein the second block (202) comprises a cache memory (202B) intended to store data of the main table used by the second algorithm (202A).

### Claim 7 (depends on 1)

The device according to claim 1, wherein the size of the first part (102) corresponds to less than 0.1% of the size of the second part (103).

### Claim 8 (depends on 1)

The device according to claim 1, wherein the first algorithm is a probabilistic algorithm.

### Claim 9 (depends on 1)

The device according to claim 1, wherein said memory device (10) further comprises a protection memory block (200) wherein an initial table implemented by the first algorithm is stored, advantageously, the first block (201) also comprises a cache memory intended to store data of the initial table implemented by the first algorithm (201A).

### Claim 10 (depends on 9)

The device according to claim 9, wherein the protection memory block (200) comprises a memory immune to the row-hammering effect, in particular said memory comprises at least one of the memories chosen from: a memory of SRAM type, a memory of the MRAM type, a memory of the CNRAM type.

### Claim 11 (depends on 9)

The device according to claim 9, wherein the protection memory block (200) comprises a DRAM memory, and wherein the memory rows are arranged so as to prevent any row-hammering within said block.

### Claim 12

A DRAM memory controller (1000), the controller being intended to configure a protection of DRAM memories against a memory row-hammering effect, the protection involving the implementation of a control circuit (1200) and a protection memory block (1101) having a predetermined capacity, the controller being adapted to:
determine the total capacity of the DRAM memories controlled by the controller (1000);
if the total capacity of the DRAM memories exceeds a size, referred to as the threshold size, beyond which the protection by an algorithm implementing a single table saved in the protection memory block (1101) is impossible, the controller (1000) divides the total capacity of the DRAM memories into N parts, N≥2, each part i, for i ranging from 1 to N, N and i being integer values, and configures the control circuit (1200) to execute N protection algorithms each referred to as algorithm i, for i ranging from 1 to N, each algorithm i being intended to protect the part i from the row-hammering effect by means of a table i, each table i, for i ranging from 2 to N, being saved in part i−1, while table 1 is saved in the protection memory block (1101), if the total capacity of the DRAM memories does not exceed the threshold size, the controller configures the control circuit (1200) so that it protects said DRAM memories by means of a single algorithm that implements a table stored in the protection memory block (1101).

### Claim 13 (depends on 12)

The controller according to claim 12, wherein the capacity of the parts i increases for i ranging from 1 to N.

### Claim 14 (depends on 12)

The controller according to claim 12 wherein the protection memory block (1101) comprises a memory immune to the memory row-hammering effect, advantageously the protection memory block (1101) comprises at least one of the memories chosen from: an SRAM memory, an MRAM memory, or a CNRAM memory.

### Claim 15 (depends on 14)

The controller according to claim 14, wherein the protection memory block (1101) is comprised in the controller (1000).

### Claim 16 (depends on 12)

The controller according to claim 12, wherein the protection memory block (1101) comprises DRAM memory, advantageously, the protection memory block (1101) forms a part 0 of the DRAM memories.

### Claim 17 (depends on 12)

The controller according to claim 12, wherein the control circuit (1200) is comprised in the controller (1000).