Assemblies comprising memory cells and select gates; and methods of forming assemblies

An assembly, comprising:

• a stack comprising alternating dielectric levels and conductive levels;
• a channel material pillar extending through the stack;
• memory cells along the channel material pillar;
• an insulative level over the stack;
• a select gate configuration over the insulative level;
• a conductive interconnect extending through an uppermost surface of the channel material pillar;
• wherein the select gate configuration comprises a first conductive gate structure and a second conductive gate structure laterally spaced from one another by an intervening insulative region;
• wherein the first and second conductive gate structures have vertically-spaced conductive regions separated from one another by dielectric regions;
• and
• vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another.

An assembly, comprising:

• a stack comprising alternating dielectric levels and conductive levels;
• a channel material pillar extending through the stack;
• memory cells along the channel material pillar;
• an insulative level over the stack;
• a select gate configuration over the insulative level;
• a conductive interconnect extending through an uppermost surface of the channel material pillar;
• wherein the select gate configuration comprises a first conductive gate structure and a second conductive gate structure laterally spaced from one another by an intervening insulative region;
• an insulative layer extending through the intervening insulative region and extending over the alternating dielectric levels and conductive levels;
• and
• wherein the conductive interconnect extends into insulative layer.

An assembly, comprising:

• a stack comprising alternating dielectric levels and conductive levels;
• a channel material pillar extending through the stack;
• memory cells along the channel material pillar;
• an insulative level over the stack;
• a select gate configuration over the insulative level;
• a conductive interconnect extending through an uppermost surface of the channel material pillar;
• and
• an insulative liner against the insulative level.

An assembly, comprising:

• a stack comprising alternating dielectric levels and conductive levels;
• a channel material pillar extending through the stack;
• memory cells along the channel material pillar;
• an insulative level over the stack;
• a select gate configuration over the insulative level;
• a conductive interconnect extending through an uppermost surface of the channel material pillar;
• and
• an insulative liner over the insulative level and against an uppermost surface of the channel material pillar.

An assembly, comprising:

• a stack comprising alternating dielectric levels and conductive levels;
• a channel material pillar extending through the stack;
• memory cells along the channel material pillar;
• an insulative level over the stack;
• a select gate configuration over the insulative level;
• a conductive interconnect extending through an uppermost surface of the channel material pillar;
• and
• an insulative liner over the select gate configuration and the conductive interconnect extends through the insulative liner.

An assembly, comprising:

• a stack comprising alternating dielectric levels and conductive levels;
• a channel material pillar extending through the stack;
• memory cells along the channel material pillar;
• an insulative level over the stack;
• a select gate configuration over the insulative level;
• a conductive interconnect extending through an uppermost surface of the channel material pillar;
• and
• protective capping material over the select gate configuration and the conductive interconnect extends into the protective capping material.

An assembly, comprising:

• a stack comprising alternating dielectric levels and conductive levels;
• a channel material pillar extending through the stack;
• memory cells along the channel material pillar;
• an insulative level over the stack;
• a select gate configuration over the insulative level;
• a conductive interconnect extending through an uppermost surface of the channel material pillar;
• and
• dielectric material over the select gate configuration and the conductive interconnect extends into the dielectric material.