Apparatuses and methods to perform DQ swapping on memory
AssigneeMicron Technology, Inc.
InventorsWesley W. Borie, Dennis G. Montierth, Garth N. Grubb, Mow Yiak Goh, Anthony M. Geidl
Life of this patent
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Abstract
An exemplary memory includes a first sub-wordline (SWL) driver configured to provide first data from a memory cell array, a second SWL driver configured to provide second data from a memory cell array, and an input/output (I/O) circuit configured to receive the first data and the second data from the first and second SWL drivers, respectively. The I/O circuit including a data terminal mapping circuit configured to selectively route the first data and the second data to different respective data terminal based on a data terminal mapping setting.
Claims19
An apparatus comprising:
- a first sub-wordline (SWL) driver configured to provide first data from a memory cell array;
- a second SWL driver configured to provide second data from the memory cell array;
- and
- an input/output (I/O) circuit configured to receive the first data and the second data from the first and second SWL drivers, respectively, the I/O circuit including a data terminal mapping circuit configured to selectively route the first data and the second data to different respective data terminals based on a data terminal mapping setting.
A memory module comprising:
- first and second module data terminals;
- a memory package having first and second data terminals;
- and
- a swizzle configured to map the first and second data terminals of the memory package to the first and second module data terminals,
- wherein the memory package includes a data terminal mapping circuit configured to selectively arrange data provided to the first and second data terminals based on a mapping between the first and second data terminals of the memory package and the first and second module data terminals, and
- wherein, in response to the first data terminal being coupled to the first module data terminal and the second data terminal being coupled to the second module data terminal, the data terminal mapping circuit is configured to map first data from a first sub-wordline driver to the first data terminal and second data from a second sub-wordline driver to the second data terminal.
A method comprising:
- receiving, via a first sub-wordline (SWL) driver of a memory package, first data from a memory cell array of the memory package;
- receiving, via a second SWL driver, second data from the memory cell array;
- receiving a data terminal mapping setting;
- and
- selectively routing the first data and the second data to different respective data terminals of the memory package based on a data terminal mapping setting.
Dependencies are inferred from the claim text.