Multiplication hardware block with adaptive fidelity control system

A computational multiply and accumulate hardware block for executing a multiplication computation comprising:

• at least one non-transitory computer-readable medium storing a first operand and a second operand for the multiplication computation, wherein the first operand includes a first set of bit strings, and wherein the second operand includes a second set of bit strings;
• a fidelity control register storing a fidelity control value for the computational multiply and accumulate hardware block;
• at least one multiplier unit multiplying the first set of bit strings and the second set of bit strings in a set of temporal phases using the computational multiply and accumulate hardware block, wherein each temporal phase uses a different group of bit strings from the first set of bit strings and the second set of bit strings, wherein the fidelity control value is evaluated during the set of temporal phases, and wherein a cardinality of the set of temporal phases is determined by the fidelity control value;
• an accumulation circuit that accumulates a set of products of the set of temporal phases and the product of multiple sets of multiplication computations involving different operands;
• and
• a control register storing the fidelity control value.

A computational multiply and accumulate hardware block for executing a multiplication computation comprising:

• a means for storing a first operand and a second operand for the multiplication computation, wherein the first operand includes a first set of bit strings, and wherein the second operand includes a second set of bit strings;
• a means for setting a fidelity control value in a fidelity control register of the computational multiply and accumulate hardware block;
• a means for multiplying the first set of bit strings and the second set of bit strings in a set of temporal phases using the computational multiply and accumulate hardware block and evaluating the fidelity control value during the set of temporal phases, wherein each temporal phase uses a different group of bit strings from the first set of bit strings and the second set of bit strings, and wherein a cardinality of the set of temporal phases is determined by the fidelity control value;
• a means for changing the fidelity control value, during the set of temporal phases;
• and
• a means for accumulating, using an accumulation circuit, a set of products of the set of temporal phases and the product of multiple sets of multiplication computations involving different operands;
• wherein the fidelity control value sets a fidelity of execution of the multiplication computation.