Memory device
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Tsing Hua University
InventorsJun-Shen Wu, Chi-En Wang, Ren-Shuo Liu
Life of this patent
Estimating the term…
Abstract
A memory device is provided, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.
Claims20
A memory device, comprising:
- a memory array comprising a plurality of memory cells;
- a selection circuit configured to identify a first faulty cell and a second faulty cell that are in the plurality of memory cells, wherein a first priority of the first faulty cell is higher than a second priority of the second faulty cell according to the first faulty cell storing an exponent field of a floating-point number;
- and
- a replacement circuit configured to perform a replacing operation to replace the first and second faulty cells according to the first priority and the second priority.
A method, comprising:
- testing a memory array to identify a plurality of faulty cells in the memory array;
- identifying in the plurality of faulty cells an excluded cell that meets at least one of a plurality of conditions, wherein a first condition of the plurality of conditions indicates that a first value of an exponent in a first binary number corresponding to the excluded cell is smaller than an accurate value of the exponent in the first binary number corresponding to the excluded cell;
- and
- outputting a fault address of at least one cell of remaining cells in the plurality of faulty cells for replacing the at least one cell with a redundant cell.
A system, comprising:
- a memory device;
- and
- a neural network processor configured to access the memory device;
- wherein the memory device comprises:
- a plurality of memory cells configured to store data transmitted from/to the neural network processor;
- and
- a selection circuit configured to determine a fault address from a plurality of addresses received from a test circuit, wherein the fault address is of a faulty cell in the plurality of memory cells,
- wherein the selection circuit identifies that the faulty cell has a highest priority in a cell replacement operation when the faulty cell has a stuck-at-1 fault and stores an exponent field of a binary number.
Dependencies are inferred from the claim text.