Multilevel semiconductor device and structure with image sensors and wafer bonding

An integrated device, the device comprising:

• a first level comprising a first mono-crystal layer, said first mono-crystal layer comprising a plurality of single crystal transistors;
• an overlying oxide disposed on top of said first level;
• a second level comprising a second mono-crystal layer, said second level overlaying said oxide,
• wherein said second mono-crystal layer comprises a plurality of image sensors,
• wherein said second level is bonded to said first level comprising an oxide to oxide bond;
• a plurality of pixel control circuits;
• a third level disposed underneath said first level,
• wherein said third level comprises a plurality of third transistors,
• wherein said plurality of third transistors each comprise a single crystal channel;
• and
• a plurality of metal gate transistors.

An integrated device, the device comprising:

• a first level comprising a first mono-crystal layer, said first mono-crystal layer comprising a plurality of single crystal transistors;
• an overlying oxide disposed on top of said first level;
• a second level comprising a second mono-crystal layer, said second level overlaying said oxide,
• wherein said second mono-crystal layer comprises a plurality of image sensors,
• wherein said second level is bonded to said first level comprising an oxide to oxide bond;
• a plurality of pixel control circuits;
• a third level disposed underneath said first level,
• wherein said third level comprises a plurality of third transistors,
• wherein said plurality of third transistors each comprise a single crystal channel, and wherein said plurality of image sensors is aligned to said plurality of single crystal transistors with a less than 600 nm alignment error;
• and
• a plurality of recessed channel transistors.