US 12,395,453 B2 · Data access technologies

Abstract

Examples described herein relate to at least one processor and circuitry, when operational, to: cause a first number of processors of the at least one processor to access queues exclusively allocated for packets to be processed by the first number of processors; cause a second number of processors of the at least one processor to identify commands consistent with Non-volatile Memory Express (NVMe) over Quick User Data Protocol Internet Connections (QUIC), wherein the commands are received in the packets and the second number is based at least in part on a rate of received commands; and cause performance of the commands using a third number of processors. In some examples, the circuitry, when operational, is to: based on detection of a new connection on a first port, associate the new connection with a second port, wherein the second port is different than the first port and select at least one processor to identify and process commands received on the new connection.

Claims21

Dependent claims

A method comprising:

at a receiver system:
allocating a queue exclusively for packets that include Non-volatile Memory Express (NVMe) commands transmitted in a manner consistent with Quick User Data Protocol Internet Connections (QUIC) protocol to be processed by a first number of processors;
identifying received NVMe commands transmitted in a manner consistent with QUIC protocol by a second number of processors polling for received NVMe commands in the exclusively allocated queue, wherein the second number is based at least in part on a rate of received NVMe over QUIC commands;
performing the identified NVMe over QUIC commands using the processors of the first number of processors;
detecting whether a packet received on a first ingress port is associated with an existing NVMe queue pair connection or a new NVMe queue pair connection;
and
based on detection of the new NVMe queue pair connection on the first ingress port, associating a second NVMe queue pair connection with a second ingress port for receipt of packets of the new NVMe queue pair connection, wherein the second ingress port is different than the first ingress port.

4 more elements

At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:

access queues exclusively allocated for packets that include Non-volatile Memory Express (NVMe) commands transmitted in a manner consistent with Quick User Data Protocol Internet Connections (QUIC) protocol and
identify received NVMe commands transmitted in a manner consistent with QUIC protocol by a first number of processors polling for received NVMe commands in the exclusively allocated queue, wherein the first number is based at least in part on a rate of received NVMe over QUIC commands;
perform the identified NVMe over QUIC commands using a second number of processors;
detect whether a packet received on a first ingress port is associated with an existing NVMe queue pair connection or a new NVMe queue pair connection;
and
based on detection of the new NVMe queue pair connection on the first ingress port, associate a second NVMe queue pair connection with a second ingress port for receipt of packets of the new NVMe queue pair connection, wherein the second ingress port is different than the first ingress port.

3 more elements

Dependencies are inferred from the claim text.

Data access technologies

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Data access technologies

Life of this patent

Abstract

Claims21