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US 12,395,311 B2Granted
Reliable link management for a high-speed signaling interconnect
AssigneeNVIDIA Corporation
InventorsSeema Kumar, Ish Chadha
Life of this patent
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Abstract
A device includes receiver circuitry to receive incoming signals on a clock lane and data lanes and detection circuitry. The detection circuitry is to monitor the incoming signals on the clock lane, and determine that an incoming pattern of the incoming signals on the clock lane does not correspond to a clock pattern associated with communicating data on the data lanes. The detection circuitry is to initiate a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern.
Claims20
A device comprising:
- receiver circuitry to receive incoming signals on a clock lane and data lanes, wherein the clock lane and data lanes are part of a Ground Reference Signaling (GRS) link, wherein the incoming signals on the clock lane comprise a forwarded clock associated with data signals on the data lanes of the GRS link, wherein the GRS link comprises a clock pattern on the clock lane, the clock pattern being associated with communicating data on the data lanes;
- and
- detection circuitry to:
- monitor the incoming signals on the clock lane;
- determine that an incoming pattern of the incoming signals on the clock lane does not correspond to the clock pattern associated with communicating data on the data lanes;
- and
- initiate a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern.
4 more elements
A device comprising:
- receiver circuitry to receive incoming signals on a clock lane and data lanes;
- and
- detection circuitry to:
- monitor the incoming signals on the clock lane;
- determine that an incoming pattern of the incoming signals on the clock lane does not correspond to a clock pattern associated with communicating data on the data lanes;
- and
- initiate a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern, wherein the incoming signals on the clock lane comprise a forwarded clock, and wherein, to determine that the incoming pattern of the incoming signals on the clock lane does not correspond to the clock pattern, the detection circuitry is to identify a static pattern in the forwarded clock.
4 more elements
A device comprising:
- receiver circuitry to receive incoming signals on a clock lane and data lanes;
- and
- detection circuitry to:
- monitor the incoming signals on the clock lane;
- determine that an incoming pattern of the incoming signals on the clock lane does not correspond to a clock pattern associated with communicating data on the data lanes;
- and
- initiate a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern, wherein the incoming signals on the clock lane comprise a forwarded clock, and wherein, to determine that the incoming pattern of the incoming signals on the clock lane does not correspond to the clock pattern, the detection circuitry is to determine that the forwarded clock is no longer driven on the clock lane.
4 more elements
A method of operating a device, the method comprising:
- receiving incoming signals on a clock lane and data lanes;
- monitoring the incoming signals on the clock lane;
- determining that an incoming pattern of the incoming signals on the clock lane does not correspond to a clock pattern associated with communicating data on the data lanes;
- and
- initiating a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern, wherein the incoming signals on the clock lane comprise a forwarded clock, and wherein determining that the incoming pattern of the incoming signals on the clock lane does not correspond to the clock pattern comprises either:
- identifying a static pattern in the forwarded clock;
- or
- determining that the forwarded clock is no longer driven on the clock lane.
5 more elements
A system comprising:
- a Ground Reference Signaling (GRS) link comprising a clock lane and data lanes;
- a first device coupled to the GRS link;
- and
- a second device coupled to the GRS link, wherein the second device comprises:
- receiver circuitry to receive incoming signals on the clock lane and the data lanes, wherein the incoming signals on the clock lane comprise a forwarded clock associated with data signals on the data lanes of the GRS link, wherein the GRS link comprises a clock pattern on the clock lane, the clock pattern being associated with communicating data on the data lanes;
- and
- detection circuitry to:
- monitor the incoming signals on the clock lane;
- determine that an incoming pattern of the incoming signals on the clock lane does not correspond to the clock pattern associated with communicating data on the data lanes;
- and
- initiate a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern.
8 more elements
Dependencies are inferred from the claim text.