US 12,395,176 B2Granted

Multiple sample-rate data converter

AssigneeTektronix, Inc.

InventorsJoshua J. O'Brien, Timothy E. Bieber, Barton T. Hickman

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Abstract

A test and measurement instrument includes a first data channel including a first data converter operating at a first rate, and a second data channel including a second data converter operating at a second rate that is different than the first rate. Rate controls may include a clock generation circuit. The clock generation circuit includes an intermediate frequency generator structured to generate an intermediate frequency clock from a first clock reference signal, a first frequency clock generator structured to generate a first frequency clock directly from the intermediate frequency clock, and a second frequency clock generator structured to generate a second frequency clock directly from the intermediate frequency clock. The first frequency clock may be used to control the rate of the first data channel, and the second frequency clock may be used to control the rate of the second data channel. Methods are also described.

Claims26

Dependent claims

A test and measurement instrument, comprising:

a user interface having an input selector structured to accept an indication of a test channel or channels from a user;
an input of the test and measurement instrument configured to receive a signal from a device under test, a portion of the signal including data from the one or more test channel inputs selected by the user for sampling;
a first data channel of the input including a first data converter configurable to operate at a first sampling rate;
a second data channel of the input including a second data converter configurable to operate at a second sampling rate that is different than the first sampling rate;
a clock generation circuit, including:
an intermediate frequency generator structured to generate an intermediate frequency clock from a first clock reference signal, an operational frequency of the intermediate frequency clock being different from an operational frequency of the first clock reference signal;
a first frequency clock generator structured to generate a first frequency clock directly from the intermediate frequency clock, the first frequency clock coupled to the first data converter to cause the first data channel to operate at the first sampling rate to sample and store the signal from the device under test as a first sampled waveform, and
a second frequency clock generator structured to generate a second frequency clock directly from the intermediate frequency clock, the second frequency clock coupled to the second data converter to cause the second data channel to operate at the second sampling rate to sample and store the signal from the device under test as a second sampled waveform;
and
an output configured to send an output signal to a display, the output signal including output derived from the first sampled waveform and the second sampled waveform.

7 more elements

A method in test and measurement instrument, comprising:

receiving a first input signal from a device under test at a first sampling rate on a first input channel of the test and measurement instrument, a portion of the first input signal including data from one or more channels of the device under test selected by a user for sampling via an input selector;
receiving a second input signal from the device under test at a second sampling rate on a second input channel of the test and measurement instrument;
and
generating an intermediate frequency clock from a first clock reference signal, an operational frequency of the intermediate frequency clock being different from an operational frequency of the first clock reference signal;
generating a first frequency clock directly from the intermediate frequency clock;
applying the first frequency clock to the first input channel to cause the first input channel to operate at the first sampling rate to sample and store the first input signal from the device under test as a first sampled waveform;
generating a second frequency clock directly from the intermediate frequency clock, the second frequency clock having a different rate than the first frequency clock;
and
applying the second frequency clock to the second input channel to cause the second input channel to operate at the second sampling rate to sample and store the second input signal from the device under test as a second sampled waveform;
and
sending an output signal to a display, the output signal including output derived from both the first sampled waveform and the second sampled waveform.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/845,896Filed 21 Jun 2022 · us provisional application
Priority: 18 Jun 2021
Published: US 2022/0407523 A122 Dec 2022
Granted: 19 Aug 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 29/56016
External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor: apparatus features
H03L 7/07
Using a reference signal applied to a frequency- or phase-locked loop: using several loops, e.g. for redundant clock signal generation
G01R 13/0254
Circuits therefor: for triggering, synchronisation
G11C 29/56012
External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor: timing aspects, clock generation,…