Method and machine for examining wafers
AssigneeASML Netherlands B.V.
InventorsChien-Hung Chou, Wen-Tin Tai
Life of this patent
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Abstract
Method and machine utilizes the real-time recipe to perform weak point inspection on a series of wafers during the fabrication of integrated circuits. Each real-time recipe essentially corresponds to a practical fabrication history of a wafer to be examined and/or the examination results of at least one examined wafer of same “lot”. Therefore, different wafers can be examined by using different recipes where each recipe corresponds to a specific condition of a wafer to be examined, even these wafers are received by a machine for examining at the same time.
Claims23
An inspection apparatus for inspecting a semiconductor wafer, the inspection apparatus comprising:
- a high resolution imaging tool comprising a source configured to provide a beam for imaging a semiconductor pattern on the semiconductor wafer;
- a memory storing a set of instructions;
- and
- a processor configured to execute the set of instructions to cause the apparatus to:
- determine a similarity between a map representing the semiconductor wafer and a reference;
- determine a first inspecting plan for inspecting the semiconductor wafer according to a critical area to define an inspection area on the semiconductor wafer when a first condition is satisfied that is based on the similarity, wherein the first inspecting plan covers only a semiconductor fabrication defect inspection area defined by the map;
- acquire at least one image of the semiconductor pattern on the semiconductor wafer with the high resolution imaging tool using the first inspecting plan;
- identify semiconductor fabrication defects in the inspection area according to the at least one image;
- in response to the similarity exceeding a threshold, set a semiconductor wafer map flag value to a first value, or in response to the similarity not exceeding the threshold, set the semiconductor wafer map flag value to a second value;
- and
- construct the first inspecting plan when the semiconductor wafer map flag is the first value, or construct a second inspecting plan when the semiconductor wafer map flag is the second value.
A method of inspecting a semiconductor wafer, comprising:
- determining a similarity between a map representing the semiconductor wafer and a reference;
- determining a first inspecting plan according to a critical area to define an inspection area on the semiconductor wafer when a first condition is satisfied that is based on the similarity, wherein the first inspecting plan covers only a semiconductor fabrication defect inspection area defined by the map;
- examining the semiconductor wafer with a high resolution imaging tool using the first inspecting plan;
- identifying semiconductor fabrication defects in the inspection area according to at least one image taken by the high resolution imaging tool;
- and
- in response to the similarity exceeding a threshold, setting a semiconductor wafer map flag value to a first value;
- and
- constructing the first inspecting plan when the semiconductor wafer map flag is the first value.
A non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of an inspection apparatus to cause the inspection apparatus to perform a method for inspecting a semiconductor wafer, the method comprising:
- determining a similarity between a map representing the semiconductor wafer and a reference;
- determining a first inspecting plan according to a critical area to define an inspection area on the semiconductor wafer when a first condition is satisfied that is based on the similarity, wherein the first inspecting plan covers only a semiconductor fabrication defect inspection area defined by the map;
- examining the semiconductor wafer with a high resolution imaging tool using the first inspecting plan;
- identifying semiconductor fabrication defects in the inspection area according to at least one image taken by the high resolution imaging tool;
- in response to the similarity exceeding a threshold, setting a semiconductor wafer map flag value to a first value, or in response to the similarity not exceeding the threshold, setting the semiconductor wafer map flag value to a second value;
- and
- constructing the first inspecting plan when the semiconductor wafer map flag is the first value, or constructing a second inspecting plan when the semiconductor wafer map flag is the second value, the second inspecting plan covering a larger area than the first inspecting plan.
Dependencies are inferred from the claim text.