Memory system with error detection
AssigneeRambus Inc.
InventorsFrederick A. Ware, John Eric Linstadt
Life of this patent
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Abstract
A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.
Claims20
A memory device comprising:
- a memory;
- a command/address interface to receive a write address over a command/address link in association with a write command or a read address over the command/address link in association with a read command;
- a data interface to receive over a data link, write data for writing to the memory at the write address in response to the write command, and to transmit over the data link, read data from the memory at the read address in response to the read command;
- an error detection code interface to receive over an error detection code link in association with the write command, a write error code associated with the write address and the write data, and to transmit over the error detection code link in association with the read command, a read error code associated with the read address and the read data;
- and
- error detection logic to receive the write address from the command/address interface, the write data from the data interface, and the write error code from the error detection code interface and to detect a write error in at least one of the write address and the write data based on the write error code.
A method for operating a memory device, the method comprising:
- receiving, by a command/address interface over a command/address link from a memory controller, a write address associated with a write command;
- receiving, by a data interface over a data link, write data for writing to a memory at the write address in response to the write command;
- receiving, by an error detection code interface over an error detection code link, a write error code associated with the write address and the write data;
- performing, by error detection logic, an error detection to detect a write error in at least one of the write address and the write data;
- outputting an error detection result based on the error detection;
- receiving, by the command/address interface over a command/address link from the memory controller, a read address associated with a read command;
- transmitting, by the data interface over the data link to the memory controller, read data from the memory at the read address in response to the read command;
- and
- transmitting, by the data interface over the error detection code link to the memory controller, a read error code associated with the read address and the read data.
A memory device comprising:
- storing means;
- a command/address receiving means for receiving a write address over a command/address link in association with a write command or a read address over the command/address link in association with a read command;
- data communicating means for receiving over a data link, write data for writing to the storing means at the write address in response to the write command, and for transmitting over the data link, read data from the storing means at the read address in response to the read command;
- error detection code communicating means for receiving over an error detection code link in association with the write command, a write error code associated with the write address and the write data, and for transmitting over the error detection code link in association with the read command, a read error code associated with the read address and the read data;
- and
- error detection means for receiving the write address from the command/address receiving means, the write data from the data communicating means, and the write error code from the error detection code communicating means, and for detecting a write error in at least one of the write address and the write data based on the write error code.
Dependencies are inferred from the claim text.