Row hammer mitigation using hierarchical detectors
AssigneeMicron Technology, Inc.
InventorsEdmund J. Gieske, Cagdas Dirik, Robert M. Walker
Life of this patent
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Abstract
An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can include row hammer detection circuitry configured to receive signaling indicative of a row activation command having a row address, increment a row counter corresponding to the row address stored in a stored in a data structure in a register or storage device, determine whether the incremented row counter is greater than a row hammer threshold, and issue a row hammer mitigation command to mitigate row hammer.
Claims20
An apparatus, comprising:
- a number of memory devices;
- and
- a memory controller coupled to one or more of the number of memory devices, the memory controller including, interface management circuitry, a first row hammer detector;
- and
- a second row hammer detector;
- and wherein the memory controller is configured to:
- receive signaling indicative of a row activation command and a row address;
- increment a row counter corresponding to the row address stored in a data structure of the first row hammer detector coupled to the controller;
- determine that the incremented row counter is greater than a row hammer threshold (RHT);
- and
- responsive to determining that the incremented row counter is greater than the first RHT, issue a row hammer mitigation command to perform row hammer detection with the second row hammer detector.
A method, comprising:
- receiving, at interface management circuitry of a memory controller of a memory sub-system, signaling indicative of a row activation command having a row address, wherein the interface management circuitry is configured for a non-deterministic memory protocol;
- incrementing a row counter corresponding to the row address stored in a data structure of a first row hammer detector included in a plurality of row hammer detectors of the memory controller;
- determining, at the memory controller, whether the incremented row counter is greater than a first row hammer threshold (RHT) of a first row hammer detector;
- and
- responsive to determining that the incremented row counter is greater than the first RHT, issuing a row hammer mitigation command to a second row hammer detector, to perform row hammer detection with the second row hammer detector.
A memory controller, comprising:
- interface management circuitry configured for a non-deterministic memory protocol;
- a first row hammer detector;
- and
- a second row hammer detector;
- and wherein the memory controller is configured to:
- receive, via the interface management circuitry, signaling indicative of a row activation command having a row address in a memory device;
- increment a row counter corresponding to the row address stored in a first data structure of the first row hammer detector;
- determine when an incremented row counter is greater than a first row hammer threshold of the first row hammer detector;
- and
- responsive to determining that the incremented row counter is greater than the first row hammer threshold, issue a row hammer mitigation command to perform row hammer detection with the second row hammer detector.
Dependencies are inferred from the claim text.