Time-division multiplexing for superconducting memory

A memory output circuit for selectively propagating proximate memory output data in a memory array of superconducting memory cells, the memory output circuit comprising:

• a plurality of datum inputs adapted to operably receive a corresponding plurality of memory state signals from physically adjacent bit lines in the memory array;
• at least one logic gate configured to implement logical OR functionality, the logic gate including a plurality of inputs, adapted to receive at least a subset of the plurality of datum inputs operatively coupled thereto, and an output adapted to propagate at least one datum output signal;
• and
• at least one delay element operatively coupled to a corresponding one of the plurality of datum inputs, the delay element being configured to generate an output signal operably connected to a corresponding one of the plurality of inputs of the logic gate, the output signal generated by the delay element being a temporal sequence of at least a subset of the memory state signals supplied thereto delayed by a prescribed delay value.