Memory graphics processing unit
AssigneeMemComputing, Inc.
InventorFabio Lorenzo Traversa
Life of this patent
Estimating the term…
Abstract
Memory graphics processing units (GPUs) are provided. In one aspect, a GPU for massive parallel processing of at least part of an image includes a plurality of pixel processing cores, each of the pixel processing cores configured to process a pixel of the image, and each of the pixel processing cores comprising a plurality of bit processing cores each configured to process a bit of the image and a plurality of address lines configured to provide access to the bit processing cores. The pixel processing cores are configured to process pixels of the image in parallel.
Claims21
A graphics processing unit (GPU) for massive parallel processing of at least part of an image, comprising:
- a plurality of pixel processing cores, each of the pixel processing cores configured to process a pixel of the image, and each of the pixel processing cores comprising a plurality of bit processing cores each configured to process an individual bit of the pixel, each of the bit processing cores comprising internal circuits;
- a plurality of address lines configured to provide access to the bit processing cores;
- and
- a plurality of interconnect lines configured to connect the bit processing cores,
- wherein the pixel processing cores are configured to process pixels of the image in parallel, and wherein each of the bit processing cores is configured to perform different binary operations on the individual bit of the pixel by selectively connecting:
- i) the internal circuits within the bit processing core and ii) the bit processing core to an adjacent bit processing core of the bit processing cores via at least one of the plurality of interconnect lines.
A graphics processing unit (GPU) for massive parallel processing of at least part of an image, comprising:
- a plurality of processing cores each configured to process an individual bit of the image, each of the plurality of processing cores comprising electronic circuits configured to store information and to process the information;
- and
- a plurality of interconnect lines configured to connect the plurality of processing cores;
- wherein the plurality of processing cores are arranged such that individual pixels of the image are processed in parallel, and
- wherein each of the processing cores is configured to perform different binary operations on the individual bit of the pixel by selectively connecting:
- i) the electronic circuits within the bit processing core and ii) the bit processing core to an adjacent processing core of the processing cores via at least one of the plurality of interconnect lines.
A method of parallel processing of image data, comprising:
- moving image data representing at least part of an image from a memory to a memory graphics processing unit (GPU), the memory GPU comprising a plurality of processing cores, and each of the processing cores comprising a plurality of bit processing cores each configured to process an individual bit of a pixel, each of the bit processing cores comprising internal circuits;
- processing the image data to perform a graphic function including a plurality of processing tasks on different parts of the image data in parallel within the memory GPU, the processing tasks comprising different binary operations, and performing the different binary operations comprises:
- performing one of the different binary operations on the individual bit of the pixel by selectively connecting:
- i) two of the processing cores together via one or more address lines and ii) two or more of the internal circuits of one of the processing cores together, and storing a result of the one of the different binary operations in a buffer;
- and
- moving the processed image data from the memory GPU to the memory.
Dependencies are inferred from the claim text.