System and method to accelerate reduce operations in graphics processor
AssigneeIntel Corporation
InventorsYong Jiang, Yuanyuan Li, Jianghong Du, Kuilin Chen, Thomas A. Tetzlaff
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Abstract
Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and broadcast a result of an operation specified in association with the barrier synchronization request.
Claims20
A graphics processor comprising:
- a memory device;
- and
- a graphics processor core coupled with the memory device, the graphics processor core having circuitry including:
- instruction execution circuitry to execute instructions;
- and
- a message gateway associated with the instruction execution circuitry, the message gateway to synchronize threads within thread group executed via the instruction execution circuitry, the message gateway configured to perform a merged write, barrier, and read operation in response to a synchronization request received from the instruction execution circuitry, the merged write, barrier, and read operation to accelerate a reduce operation associated with a set of map operations.
A method of performing a work group barrier operation for a group of threads within a graphics processor, the method comprising:
- receiving a barrier message including source data from a set of barrier requester threads in a thread work group;
- determining an operation to perform based on the barrier message;
- synchronize the set of barrier requester threads in the thread work group;
- performing the operation on the source data;
- and
- broadcasting a response including a result of the operation to the set of barrier requester threads.
A computing device comprising;
- first circuitry to execute multiple threads associated with a general-purpose graphics processing operation;
- and
- second circuitry to enable synchronization between the multiple threads via a merged write, barrier, and read operation, the merged write, barrier, and read operation to accelerate a reduce operation associated with a set of map operations performed via the first circuitry.
Dependencies are inferred from the claim text.