Atomic instruction set and architecture with bus arbitration locking

An article of manufacture comprising a non-transitory machine-readable medium, the medium comprising instructions, the instructions, when read and executed by a processor, cause the processor to:

• identify a first input instruction in a code stream to be executed;
• determine that the first input instruction specifies an atomic operation designation to atomically execute the first input instruction and a second input instruction to immediately follow the first input instruction in the code stream;
• determine that that the first input instruction specifies an access by an initiator of a target;
• based on a determination that the first input instruction specifies the atomic operation designation to atomically execute the first input instruction and a second input instruction to immediately follow the first input instruction in the code stream, lock a bus between the initiator and the target for a duration of execution of the first input instruction and the second input instruction;
• and
• execute the first input instruction.

A method, comprising, at a processor:

• identifying a first input instruction in a code stream to be executed;
• determining that the first input instruction specifies an atomic operation designation to atomically execute the first input instruction and a second input instruction to immediately follow the first input instruction in the code stream;
• based on a determination that the first input instruction specifies the atomic operation designation to atomically execute the first input instruction and a second input instruction to immediately follow the first input instruction in the code stream, selectively blocking interrupts for a duration of execution of the first input instruction and the second input instruction;
• and
• executing the first input instruction.

A method, comprising:

• identifying a first input instruction in a code stream to be executed;
• determining that the first input instruction includes an access by an initiator of a target;
• determining that the first input instruction specifies an atomic operation designation to atomically execute the first input instruction and a second input instruction to immediately follow the first input instruction in the code stream;
• based on a determination that the first input instruction specifies the atomic operation designation to atomically execute the first input instruction and a second input instruction to immediately follow the first input instruction in the code stream, locking a bus between the initiator and the target for a duration of execution of the first input instruction and the second input instruction;
• and
• executing the first input instruction.