Substrate current suppression circuit, reference voltage generation circuit, and semiconductor device

A substrate current suppression circuit comprising:

• a semiconductor substrate of a first polarity, the semiconductor substrate including a first principal surface and a second principal surface on opposite sides;
• a first transistor, a second transistor, a third transistor, and a fourth transistor on a first principal surface side of the semiconductor substrate;
• and
• a fixed voltage line that supplies a fixed voltage to a collector of the third transistor and a collector of the fourth transistor, wherein
• each of a collector of the first transistor and a collector of the second transistor is connected to a substrate region of the first polarity on a second principal surface side in the semiconductor substrate,
• a polarity of the third transistor is opposite to a polarity of the first transistor,
• a polarity of the fourth transistor is opposite to a polarity of the second transistor, and
• the fixed voltage is a voltage higher than a base voltage of the third transistor and the fourth transistor when the first polarity is p type, and is a voltage lower than the base voltage when the first polarity is n type.