A method for making gates of different sizes, comprising:
- step 1, providing a substrate, forming a first polysilicon layer on the substrate, forming a hard mask layer on the first polysilicon layer, forming a silicon oxide layer on the hard mask layer, forming a second polysilicon layer on the silicon oxide layer, configuring a region of small-sized gates, and patterning the second polysilicon layer in the region of small-sized gates to form a plurality of dummy gate structures;
- step 2, defining a minimum width of one of the small-sized gates, and forming spacers on sidewalls of each of the plurality of dummy gate structures, wherein a width of the spacer is configured to be the minimum width of one of the small-sized gates;
- step 3, removing the plurality of dummy gate structures;
- step 4, configuring a region of large-sized gates, and spin-coating a silicon-on-carbon (SOC) layer to cover the spacers of the region of small-sized gates and cover the region of large-sized gates;
- step 5, etching the SOC layer and the silicon oxide layer, wherein the etching stops at an upper surface of the hard mask layer, exposing the spacers of each one of the plurality of dummy gate structures, wherein the post etching SOC layer forms a first SOC pattern structure and a second SOC pattern structure, wherein the first SOC pattern structure covers two spacers of each one of the plurality of dummy gate structures, wherein the second SOC pattern structure is configured to be in the region of large-sized gates, and wherein a width of the second SOC pattern structure is configured to a width of one of the large-sized gates;
- step 6, providing a photomask comprising a medium-sized gate width for the small-sized gates, wherein the medium-sized gate width is in a range between a small-sized gate width and the width of the one of the large-sized gates;
- and performing photolithography and etching on the first SOC pattern structure by applying the photomask, wherein a third SOC pattern structure is formed after the etching, wherein one side of the third SOC pattern structure covers one side of one of the spacers of each one of the plurality of dummy gate structures, the other side of the spacer not covered by the third SOC pattern structure is configured to define one side of the gate with the medium-sized gate width, and wherein an outer side of the third SOC pattern structure is configured to define another side of the gate with the medium-sized gate width;
- step 7, etching the hard mask layer to form a hard mask pattern, with the spacer exposed from step 5, the outer side of the third SOC pattern structure in step 6, the other side of the spacer abutting the third SOC pattern structure, and sidewalls of the second SOC pattern structure;
- and
- step 8, etching the first polysilicon layer masked by the sidewalls of the hard mask pattern, to form the gates with the minimum width, the medium-sized gate width, and the width of the one of the large-sized gates.