# US 12,389,544 B2 · Method of making a stacked electronic component

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- Number: US 12,389,544 B2
- Document ID: US12389544B2
- Status: Granted
- Kind: B2
- Application number: 17/950,359
- Filed: 2022-09-22
- Published: 2023-01-19
- Granted: 2025-08-12
- Earliest claimed: 2021-01-11
- Assignees: X-Celeprint Limited
- Applicants: X-Celeprint Limited
- Inventors: Ronald S. Cok
- Web page: https://patentgrep.com/patent/US12389544B2

## CPC

- H05K 1/182: associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
- H05K 1/0243: {Printed circuits associated with mounted high frequency components}
- H05K 1/0284: {Details of three-dimensional rigid printed circuit boards (H05K1/119 takes precedence; shaping of the substrate H05K3/0014)}
- H05K 1/11: Printed elements for providing electric connections to or between printed circuits
- H05K 1/162: {incorporating printed capacitors}
- H05K 1/165: {incorporating printed inductors}
- H05K 1/167: {incorporating printed resistors}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 90/00: Package configurations
- H05K 2201/09263: Meander
- H05K 2201/09763: Printed component having superposed conductors, but integrated in one circuit layer
- H10W 44/248: {for antennas}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 90/20: Configurations of stacked chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/732: {between stacked chips}
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A stacked electronic component comprises a stack of three or more print layers. Each print layer has an area less than any print layers beneath the print layer in the stack. Each print layer comprises a dielectric layer and a functional layer disposed on the dielectric layer. The functional layer comprises an exposed conductive portion that is not covered with a dielectric layer of any of the print layers and each exposed conductive portion is nonoverlapping with any other exposed conductive portion. A patterned electrode layer is coated on at least a portion of the stack and defines one or more electrodes. Each electrode of the one or more electrodes in electrical contact with an exclusive subset of the exposed conductive portions. The functional layers can be passive conductors forming capacitors, resistors, inductors, or antennas, or active layers forming electronic circuits.

## Claims

### Claim 1

A method of making a stacked electronic component, comprising:
providing one or more print-layer source wafers each comprising multiple print layers, each of the print layers comprising a dielectric layer and a functional layer disposed on the dielectric layer, each functional layer comprising an exposed conductive portion that is not covered with a dielectric layer of any of the print layers;
providing a component source substrate;
transfer printing a first print layer from one of the one or more print-layer source wafers onto the component source substrate;
transfer printing a second print layer from one of the one or more print-layer source wafers onto the first print layer to form a stack of print layers;
transfer printing a third print layer from one of the one or more print-layer source wafers onto the second print layer thereby increasing the number of print layers in the stack of print layers;
after printing the third print layer onto the stack of print layers, coating the stack of print layers with an electrode layer; and
patterning the electrode layer to define one or more electrodes, the one or more electrodes in electrical contact with each exposed conductive portion of an exclusive subset of the print layers in the stack to make the stacked electronic component,
wherein the second print layer has a smaller area than the first print layer and the third print layer has a smaller area than the second print layer and each exposed conductive portion of the print layers in the stack is nonoverlapping with any other exposed conductive portion.

### Claim 2 (depends on 1)

The method of claim 1, further comprising successively transfer printing print layers having successively smaller areas from a print-layer source wafer of the one or more print-layer source wafers onto the stack to increase the number of print layers in the stack, wherein each functional layer comprises the exposed conductive portion that is not covered with the dielectric layer of any of the print layers.

### Claim 3 (depends on 1)

The method of claim 1, wherein the one or more print-layer source wafers are a single, common print-layer source wafer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising rotating the second print layer with respect to the first print layer while transfer printing the second print layer onto or over the first print layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the method further comprises providing a target substrate and transfer printing the stacked electronic component to the target substrate.

### Claim 6 (depends on 1)

The method of claim 1, further comprising coating the electrode layer with an insulating layer and forming vias in the insulating layer to expose the exposed conductive portions.

### Claim 7 (depends on 1)

The method of claim 1, wherein patterning the electrode layer comprises forming a functional-layer connector that electrically connects the exposed conductive portions of at least two print layers in the stack and is physically and spatially separate from the one or more electrodes so that the one or more electrodes electrically connect fewer than all of the exposed conductive portions in the stack.