Holdover mode device, method and measurement and adjustment module

A holdover mode method, comprising:

• detecting whether a time synchronization source is abnormal;
• when the time synchronization source is not abnormal, using the time synchronization source as an input clock (IN[n]) of a digital PLL to lock an output clock (OUT[n]) of the digital PLL to be the input clock (IN[n]) of the digital PLL, transmitting the output clock (OUT[n]) to at least one hardware module, calculating a variation of a frequency difference between the time synchronization source and a reference clock (CLK[n]) which is generated by an adjustable oscillator and provided to the digital PLL, and building a frequency difference prediction model according to the variation of the frequency difference;
• and
• when the time synchronization source is abnormal, using a buffered time synchronization source as the input clock (IN[n]) of the digital PLL to lock the output clock (OUT[n]) of the digital PLL to be the input clock (IN[n]) of the digital PLL, transmitting the output clock (OUT[n]) to the at least one hardware module, using the frequency difference prediction model to calculate a predicted variation of the frequency difference according to multiple buffered frequency difference values, and adjusting the reference clock (CLK[n]) which is generated by an adjustable oscillator and provided to the digital PLL according to the predicted variation of the frequency difference;
• wherein the predicted variation of the frequency difference comprises multiple predicated frequency difference values in at least next 8 to 24 hours, and in a holdover mode, in the at least next 8 to 24 hours, a difference between a drift of the output clock (OUT[n]) and the time synchronization source is within 1500 nanoseconds.

A measurement and adjustment module, used in a holdover mode device, comprising:

• a frequency difference measurement unit, configured to calculate a variation of a frequency difference between a time synchronization source and a reference clock (CLK[n]) which is generated by an adjustable oscillator and provided to a digital PLL when the time synchronization source is abnormal;
• and
• a frequency difference prediction unit, electrically connected to the frequency difference measurement unit;
• wherein when the time synchronization source is not abnormal, the frequency difference prediction unit builds a frequency difference prediction model according to the variation of the frequency difference, and buffers multiple frequency difference values of the variation of the frequency difference;
• wherein when the time synchronization source is abnormal, the frequency difference prediction unit uses the frequency difference prediction model to calculate a predicted variation of the frequency difference according to the buffered frequency difference values, and generates the adjustment signal according to the predicted variation of the frequency difference;
• wherein the predicted variation of the frequency difference comprises multiple predicated frequency difference values in at least next 8 to 24 hours, and in a holdover mode, in the at least next 8 to 24 hours, a difference between a drift of the output clock (OUT[n]) and the time synchronization source is within 1500 nanosecond.