Timer-based resolver integral demodulation

A digital signal processing system to determine a position of a resolver, the system comprising:

• a digital signal processor that includes first timer and second timer, wherein the first timer creates a resolver excitation signal from a series of samples and creates an incrementing Select/Zero Crossing signal each the resolver excitation signal crosses zero;
• a multiplexer configured to receive resolver sine and resolver cosine signals from the resolver that are based on the excitation signal, the multiplexer having a select input receiving the Select/Zero Crossing signal;
• an analog to digital converter connected to an output of the multiplexer, the analog to digital converter having an output connected to the second timer;
• and
• a memory buffer connected to the second timer that includes a sine sample buffer and a cosine sample buffer;
• wherein when the Select/Zero Crossing signal has a first value, the multiplexer provides the resolver sine signal to the analog to digital converter to convert the resolver sine signal to a series of digital sine samples, and the second timer stores the series of digital sine samples in the sine sample buffer;
• and
• wherein when the Select/Zero Crossing signal has a second value, the multiplexer provides the resolver cosine signal to the analog to digital converter to convert the resolver cosine signal to a series of digital cosine samples, and the second timer storing the series of digital cosine samples in the cosine sample buffer.