Clock and data recovery circuit with spread spectrum clocking synthesizer

A circuitry, comprising:

• a phase-locked loop, configured to generate a first clock signal with spread-spectrum clocking (SSC) modulation and a control signal;
• a clock and data recovery (CDR) circuit, comprising:
• a phase detector, configured to generate a detection result according an input signal and an output clock signal, wherein the input signal is with SSC modulation;
• a digital loop filter, coupled to the phase detector, configured to filter the detection result to generate a filtered signal;
• and
• a first phase interpolator, configured to generate the output clock signal according to the filtered signal and a second clock signal;
• and
• a second phase interpolator, configured to cancel an SSC component contributed by the first clock signal to generate the second clock signal according to the control signal,
• wherein the second phase interpolator is positioned between the PLL and the first phase interpolator, and the second phase interpolator is configured to adjust a phase of the first clock signal to generate the second clock signal, and the first phase interpolator is configured to adjust a phase of the second clock signal to generate the output clock signal according to the filtered signal.