Programmable delay-line circuit with single delay array and real-time calibration
AssigneeQUALCOMM Incorporated
InventorsWenjing Yin, Xu Zhang, Qingjin Du
Life of this patent
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Abstract
A programmable delay-line circuit is provided that includes a single ring oscillator that is calibrated continuously by a calibration logic circuit. A clock edge sampler samples an input clock responsive to a plurality of oscillator output signals from the ring oscillator to form a corresponding plurality of data output signals. A clock edge voter processes the data output signals to identify a first one of the oscillator output signals that samples an edge transition of the input clock. Based upon a desired delay, a decoder selects for a second one of the oscillator output signals to produce an output clock signal.
Claims20
A delay-line circuit for delaying an input clock signal, comprising:
- a ring oscillator including a plurality of delay cells, the ring oscillator configured to produce oscillator output signals;
- a clock edge sampler configured to generate data output signals, the clock edge sampler including a plurality of flip-flops corresponding to the plurality of delay cells on a one-to-one basis, each flip-flop being configured to latch the input clock signal responsive to an oscillator output signal from a corresponding delay cell to produce a corresponding data output signal;
- and
- a delay output decoder configured to process the data output signals to select a first one of the oscillator output signals to form an output clock signal.
A method, comprising:
- generating a corresponding oscillator output signal in each delay cell in a plurality of delay cells arranged to form a ring oscillator;
- sampling an input clock signal responsive to each oscillator output signal to form a plurality of data output signals;
- processing the plurality of data output signals to identify a first one of the oscillator output signals as sampling an edge transition of the input clock signal;
- and
- outputting a second one of the oscillator output signals as an output clock signal.
A delay-line circuit, comprising:
- a single ring oscillator configured to produce a plurality of oscillator output signals;
- a clock edge sampler configured to sample an input clock signal according to the plurality of oscillator output signals to provide a plurality of data output signals;
- and
- a decoder configured to select one of the oscillator output signals as an output clock signal responsive to a processing of the plurality of data output signals.
Dependencies are inferred from the claim text.