Non-volatile memory with lower current program-verify
AssigneeSanDisk Technologies LLC
InventorsAbu Naser Zainuddin, Jiahui Yuan, Toru Miwa
Life of this patent
Estimating the term…
Abstract
A memory system programs memory cells connected to a selected word line by applying doses of programming and performing program-verify between doses. An efficient and low current program-verify operation includes: while scanning the results of a previous program-verify operation, ramp up voltages on the select lines for the next program-verify operation without waiting for the scan to complete and ramp up voltages on unselected word lines for the next program-verify operation following a step signal (so that voltage applied to the unselected word lines rise in steps) without waiting for the scan to complete.
Claims20
A non-volatile storage apparatus, comprising:
- a plurality of non-volatile memory cells;
- a plurality of word lines connected to the memory cells;
- a first select line connected to the memory cells;
- and
- a control circuit connected to the memory cells and word lines as well as the first select line, the control circuit is configured to program the memory cells by applying doses of programming and perform program-verify between doses of programming;
- the control circuit is configured to perform program-verify between doses of programming by:
- ramping up voltage on the first select line for a next program-verify operation while performing a scan of the results of a previous program-verify operation and without waiting for the scan to complete;
- and
- ramping up the voltages on unselected word lines for the next program-verify operation following a step signal while performing a scan of the results of a previous program-verify operation and without waiting for the scan to complete.
A method, comprising:
- applying doses of programming to a set of non-volatile memory cells connected to a selected word line;
- and
- performing program-verify between the doses of programming including testing for a lower verify level for a data state and testing for a higher verify level for the data state, the testing for a higher verify level for the data state comprises:
- ramping up voltages on a select line in order to test for the higher verify level while performing a scan of the results of the testing for the lower verify level and without waiting for the scan to complete;
- and
- ramping up the voltages on unselected word lines in order to test for the higher verify level while performing the scan of the results of the testing for the lower verify level and without waiting for the scan to complete.
A non-volatile storage apparatus, comprising:
- a plurality of non-volatile memory cells;
- a plurality of word lines connected to the memory cells;
- a select line connected to the memory cells;
- and
- a control circuit connected to the memory cells and word lines as well as the select line, the control circuit is configured to program the memory cells by applying a dose of programming and verify status of programming after applying the dose of programming, the verifying status of programming comprises verifying status for a lower verify level for a data state and verifying status for a higher verify level for the data state after applying the dose of programming, the verifying status for the lower verify level for the data state comprises a first sensing of memory cells to determine which memory cells have threshold voltage higher than the lower verify level and scanning results of the first sensing, the verifying status for the higher verify level for the data state comprises:
- ramping up voltage on a select line to a sensing enable voltage concurrently with, and without waiting for the completion of, the scanning results of the first sensing;
- applying a step signal to control a voltage source connected to unselected word lines;
- using the voltage source to ramp up voltage on unselected word lines to an overdrive voltage concurrently with, and without waiting for the completion of, the scanning results of the first sensing, in response to the step signal so that voltage applied to the unselected word lines rises in steps;
- applying a verify compare voltage to a selected word line;
- and
- sensing memory cells connected to the selected word line.
Dependencies are inferred from the claim text.