Structures for three-terminal memory cells

A memory structure comprising:

• a source electrode having an upper surface;
• a drain electrode having an upper surface;
• a control electrode laterally between the source electrode and the drain electrode, the control electrode has a lower surface, a first side, and a second side;
• a hole generating layer on the control electrode;
• a dielectric channel layer on the hole generating layer, the dielectric channel layer having a first side and a second side, wherein the first side contacts the source electrode and the second side contacts the drain electrode;
• a first spacer layer on the first side of the control electrode;
• a second spacer layer on the second side of the control electrode, wherein the first spacer layer and the second spacer layer isolate the source electrode and the drain electrode from the control electrode and the hole generating layer;
• a first interconnect structure below and in contact with the lower surface of the control electrode;
• a second interconnect structure above and in contact with the upper surface of the source electrode;
• and
• a third interconnect structure above and in contact with the upper surface of the drain electrode.

A memory structure comprising:

• a first dielectric region;
• a first interconnect structure in the first dielectric region;
• a second dielectric region on the first dielectric region;
• a source electrode in the second dielectric region;
• a drain electrode in the second dielectric region;
• a control electrode in the second dielectric region, the control electrode is laterally between the source electrode and the drain electrode, the control electrode has a lower surface, a first side, and a second side, wherein the lower surface of the control electrode is on the first interconnect structure;
• a hole generating layer in the second dielectric region, the hole generating layer is on the control electrode;
• a dielectric channel layer in the second dielectric region, the dielectric channel layer is on the hole generating layer, the dielectric channel layer having a first side and a second side, wherein the first side contacts the source electrode and the second side contacts the drain electrode;
• a first spacer layer in the second dielectric region, the first spacer layer is on the first side of the control electrode;
• a second spacer layer in the second dielectric region, the second spacer layer is on the second side of the control electrode, wherein the first spacer layer and the second spacer layer isolate the source electrode and the drain electrode from the control electrode and the hole generating layer;
• a third dielectric region on the second dielectric region;
• a second interconnect structure in the third dielectric region, the second interconnect structure is on the source electrode;
• and
• a third interconnect structure in the third dielectric region, the third interconnect structure is on the drain electrode.