Memory chips and operating methods thereof

Abstract

This disclosure discloses a memory chip and an operating method thereof. The operating method incudes: determining whether a quantity of one or more written memory units in a storage space of the one or more storage spaces is less than or equal to a preset quantity or a write address corresponding to a write instruction is smaller than one of storage addresses of the storage space; in response to determining that the quantity of the one or more written memory units in the storage space is less than or equal to the preset quantity or the write address corresponding to the write instruction is smaller than the one of storage addresses of the storage space, determining an operating state of the storage space as a part programmed state; and disabling an error correction mechanism for the storage space in the part programmed state.

Dependencies are inferred from the claim text.