Delayed snoop for improved multi-process false sharing parallel thread performance
AssigneeTexas Instruments Incorporated
InventorsKai Chirca, Timothy David Anderson
Life of this patent
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AssigneeTexas Instruments Incorporated
InventorsKai Chirca, Timothy David Anderson
Estimating the term…
Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.
A device comprising:
A device comprising:
Dependencies are inferred from the claim text.