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US 12,386,618 B2Granted
Multi-buffered register files with shared access circuits
AssigneeIntel Corporation
InventorsSteven Hsu, Amit Agarwal, Debabrata Mohapatra, Arnab Raha, Moongon Jung, Gautham Chinya, Ram Krishnamurthy
Life of this patent
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Abstract
Systems, apparatuses and methods identify a plurality of registers that are associated with a system-on-chip. The plurality of registers includes a first portion dedicated to write operations and a second portion dedicated to read operations. The technology writes data to the first portion of the plurality of registers, and transfers the data from the first portion to the second portion.
Claims22
A computing system comprising:
- a system-on-chip that includes a plurality of registers, and access circuitry to access the plurality of registers, wherein the plurality of registers includes a first portion dedicated to write operations and a second portion dedicated to read operations;
- and
- a memory including a set of executable program instructions, which when executed by the system-on-chip, cause the computing system to:
- write data to the first portion of the plurality of registers as part of the write operations;
- control the write operations for writing data into the first portion based on a first clock signal;
- control the read operations for reading data from the second portion based on the first clock signal;
- and
- control data transfer from the first portion to the second portion based on a second clock signal, wherein the second clock signal is different from the first clock signal.
5 more elements
A semiconductor apparatus comprising:
- one or more substrates;
- and
- logic coupled to the one or more substrates, wherein the logic is implemented in one or more of configurable logic or fixed-functionality logic hardware, the logic coupled to the one or more substrates to:
- identify a plurality of registers that is associated with a system-on-chip, wherein the plurality of registers include a first portion dedicated to write operations and a second portion dedicated to read operations;
- write data to the first portion of plurality of registers as part of the write operations;
- control the write operations for writing data into the first portion based on a first clock signal;
- control the read operations for reading data from the second portion based on the first clock signal;
- and
- control data transfer from the first portion to the second portion based on a second clock signal, wherein the second clock signal is different from the first clock signal.
6 more elements
A method comprising:
- identifying a plurality of registers that are associated with a system-on-chip, wherein the plurality of registers includes a first portion dedicated to write operations and a second portion dedicated to read operations;
- writing data to the first portion of the plurality of registers as part of the write operations;
- controlling the write operations for writing data into the first portion based on a first clock signal;
- controlling the read operations for reading data from the second portion based on the first clock signal;
- and
- controlling data transfer from the first portion to the second portion based on a second clock signal, wherein the second clock signal is different from the first clock signal.
3 more elements
Dependencies are inferred from the claim text.