Decompilation apparatus and recompilation system for a processor architecture
AssigneeFujitsu Technology Solutions GmbH
InventorsDieter Kasper, Raimund Mayer
Life of this patent
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AssigneeFujitsu Technology Solutions GmbH
InventorsDieter Kasper, Raimund Mayer
Estimating the term…
A decompilation apparatus includes a matcher that divides captured first program code for a processor of a first processor architecture into a sequence of code sections based on a predetermined set of at least partially parameterized code patterns, wherein the first program code implements a program logic and has been generated by compiling a computer program defined in a high-level language by a compiler, and the matcher captures for each code section specific parameter values for each parameter of a corresponding parameterized code pattern and assigns to each code section a terminal symbol of an intermediate language; and a parser that reduces a sequence of terminal symbols assigned to the sequence of code sections to non-terminal symbols of the intermediate language, wherein a totality of the non-terminal symbols generated by the parser by reduction describes the program logic of the computer program in the intermediate language.
A decompilation apparatus comprising:
A computer program product comprising program code stored in a memory of a computer system, wherein the program code implements a decompiler, and wherein the program code causes a processor of the computer system to perform at least steps a) and b) when the program code is executed by the processor of the computer system:
Dependencies are inferred from the claim text.