Arithmetic circuit

An arithmetic circuit that receives M (M is an integer of not less than 2) complex numbers X[m] (m=1, . . . , M) each of which is divided into a real part value x_real[m] and an imaginary part value x_imag[m] (m=1, . . . , M), and a complex number coefficient C divided into a real part value c_real and an imaginary part value c_imag, and calculates and outputs M complex number values Y[m] containing a result of real part product-sum arithmetic and a result of imaginary part product-sum arithmetic, the arithmetic circuit comprising:

• an LUT generation circuit configured to calculate a value d_sub of a difference between the real part value c_real and the imaginary part value c_imag of the complex number coefficient C, and a value d_add of a sum of the real part value c_real and the imaginary part value c_imag;
• and
• M distributed arithmetic circuits configured to calculate and output, in parallel for each of M, the complex number values Y[m] as a result of multiplying each of data, which correspond to the circuit, of the complex numbers X[m] by the complex number coefficient C and summing up the products,
• wherein each of the distributed arithmetic circuits receives the complex number X[m], the real part value c_real and the imaginary part value c_imag of the complex number coefficient C, and the values d_sub and d_add calculated by the LUT generation circuit, and calculates and outputs, in parallel for each of M, y_real[m] as a result of product-sum arithmetic c_real×x_real[m]−c_imag×x_imag[m] of the real part, and y_imag[m] as a result of product-sum arithmetic c_imag×x_real[m]+c_real×x_imag[m] of the imaginary part.