Partial block performance management
AssigneeSeagate Technology LLC
InventorAbhaykumar Kataria
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Abstract
The technology disclosed herein provides a method including receiving a plurality of host write requests at a plurality of host logical block addresses (HLBAs), determining spatial adjacency of the plurality of host LBA write requests on a media of a storage device, and in response to determining that the spatial adjacency of the plurality of host LBAs (HLBAs) write requests meets a spatial adjacency condition reading data from a plurality of storage device LBAs (DLBAs) corresponding to each of the plurality of HBLAs into a cache, modifying the read data for each of the plurality of DBLAs in the cache, and writing the modified data at each of the plurality of DBLAs during a single data write operation.
Claims20
A method, comprising:
- receiving a plurality of host write requests at a plurality of host logical block addresses (HLBAs);
- determining spatial adjacency of the plurality of host LBA write requests on a media of a storage device;
- and
- in response to determining that the spatial adjacency of the plurality of host LBAs (HLBAs) write requests meets a spatial adjacency condition:
- reading data from a plurality of storage device LBAs (DLBAs) corresponding to each of the plurality of HBLAs into a cache,
- modifying the read data for each of the plurality of DBLAs in the cache, and,
- in response to determining that the spatial adjacency of the plurality of HLBA write requests meets the spatial adjacency condition, writing the data from the plurality of HLBA write requests in a volatile memory and initiating a rude power loss execution flag, where the rude power loss execution flag initiates an operation to write the data from the plurality of HLBA write requests from the volatile memory to a section of the media of the storage device.
In a computing environment, a method performed at least in part on at least one processor, the method comprising:
- receiving a plurality of host write requests at a plurality of host logical block addresses (HLBAs);
- determining spatial adjacency of the plurality of host LBA write requests on a media of a storage device;
- and
- in response to determining that the spatial adjacency of the plurality of host LBAs (HLBAs) write requests meets a spatial adjacency condition:
- reading data from a plurality of storage device LBAs (DLBAs) corresponding to each of the plurality of HBLAs into a cache,
- modifying the read data for each of the plurality of DBLAs in the cache, and,
- in response to determining that the spatial adjacency of the plurality of HLBA write requests meets the spatial adjacency condition, writing the data from the plurality of host LBA write requests in a volatile memory and initiating a rude power loss execution flag, where the rude power loss execution flag initiates an operation to write the data from the plurality of host LBA write requests from the volatile memory to a section of the media of the storage device.
One or more non-transitory tangible computer-readable storage media encoding computer-executable instructions for executing on a computer system a computer process, the computer process comprising:
- receiving a plurality of host write requests at a plurality of host logical block addresses (HLBAs);
- determining spatial adjacency of the plurality of host LBA write requests on a media of a storage device;
- and
- in response to determining that the spatial adjacency of the plurality of host LBAs (HLBAs) write requests meets a spatial adjacency condition:
- reading data from a plurality of storage device LBAs (DLBAs) corresponding to each of the plurality of HBLAs into a cache,
- modifying read the data for each of the plurality of DBLAs in the cache, and,
- in response to determining that the spatial adjacency of the plurality of HLBA write requests meets the spatial adjacency condition, writing the data from the plurality of HLBA write requests in a volatile memory and initiating a rude power loss execution flag, where the rude power loss execution flag initiates an operation to write the data from the plurality of HLBA write requests from the volatile memory to a section of the media of the storage device.
Dependencies are inferred from the claim text.