Method for making DMOS devices including a superlattice and field plate for drift region diffusion

A method for making a double-diffused MOS (DMOS) device comprising:

• forming a semiconductor layer having a first conductivity type, and forming a lower superlattice in the semiconductor layer;
• forming a drift region of a second conductivity type in the semiconductor layer;
• forming spaced-apart source and drain regions in the semiconductor layer;
• forming an upper superlattice on the semiconductor layer;
• forming a gate above the upper superlattice;
• forming a field plate layer adjacent the drift region electrically coupled with the source region and configured to deplete the drift region;
• and
• each of the lower and upper superlattices comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

A method for making a double-diffused MOS (DMOS) device comprising:

• forming a semiconductor layer having a first conductivity type;
• forming a drift region of a second conductivity type in the semiconductor layer;
• forming spaced-apart source and drain regions in the semiconductor layer;
• forming a first superlattice on the semiconductor layer, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
• forming a gate above the first superlattice;
• forming a field plate layer extending above the gate and adjacent the drift region and configured to deplete the drift region;
• and
• forming a second superlattice in the semiconductor layer beneath the drift region, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.