Calibration method and tuning method for on-chip differential active RC filter

A calibration method for an on-chip differential active RC filter, comprising:

• obtaining a zero-crossing time of a differential signal outputted by a single-pole point real number filter by analyzing the single-pole point real number filter;
• setting a reference clock period according to a relationship between the zero-crossing time and a bandwidth of the single-pole point real number filter, and setting a calibration working time sequence according to the reference clock period;
• and
• scanning an RC configuration of an RC array according to the calibration working time sequence to realize calibration of the RC array,
• wherein scanning the RC configuration of the RC array according to the calibration working time sequence comprises:
• step one:
• arranging a pulse generation unit connected to an input terminal of the single-pole point real number filter, outputting a pulse signal by the pulse generation unit according to the calibration working time sequence, and presetting an RC configuration for the RC array;
• step two:
• sampling, through a comparator, the differential signal outputted by the single-pole point real number filter according to the pulse signal, and obtaining a comparison result;
• step three:
• determining a size relationship between a current bandwidth of the single-pole point real number filter and a target bandwidth of the single-pole point real number filter according to the comparison result;
• and
• step four:
• setting a next set of RC configuration in the RC array by using a successive approximation algorithm, repeating step two and step three;
• until an operation of the successive approximation algorithm is finished, so that an RC configuration with a bandwidth closest to the target bandwidth is obtained, and completing the calibration of the RC array,
• wherein a compensation unit is arranged according to an operational amplifier delay of an operational amplifier in the single-pole point real number filter, so that the comparator is delayed based on the operational amplifier delay and then the comparator samples the differential signal of the single-pole point real number filter,
• wherein the compensation unit is an inverter chain configured to perform a fixed delay on a comparator sampling control signal to cancel the operational amplifier delay,
• wherein the pulse generation unit is composed of a resistive voltage divider structure and two switch groups with opposite phases,
• wherein the resistive voltage divider structure is composed of two resistors Ra and one resistor Rb, one terminal of one of the two resistors Ra acts as a power terminal of the resistive voltage divider structure, and one terminal of the resistor Rb acts as a ground terminal of the resistive voltage divider structure, the two resistors Ra and the one resistor Rb are sequentially connected in series between the power terminal and the ground terminal, the power terminal also acts as a first direct current (DC) signal terminal, one terminal that the two resistors Ra are connected with each other is a common-mode reference voltage terminal, and one terminal that one of the two resistors Ra connected to the resistor Rb acts as a second DC signal terminal,
• wherein the two switch groups are composed of a third switch group and a fourth switch group whose switching state is opposite to that of the third switch group;
• the third switch group is composed of a first switch and a second switch, and two terminals of the first switch are respectively connected to the first DC signal terminal and a first input terminal of the single-pole point real number filter in one-to-one manner;
• two terminals of the second switch are respectively connected to the second DC signal terminal and a second input terminal of the single-pole point real number filter in one-to-one manner;
• the fourth switch group is composed of a third switch and a fourth switch, and two terminals of the third switch are respectively connected to the first DC signal terminal and the second input terminal of the single-pole point real number filter in one-to-one manner, two terminals of the fourth switch are respectively connected to the second DC signal terminal and the first input terminal of the single-pole point real number filter in one-to-one manner.