Display device and pixel circuit thereof

An apparatus for controlling driving of an array of subpixels divided into k groups of subpixels, where k is an integer larger than 1, the apparatus comprising:

• a control signal generating module configured to provide a plurality of control signals to one or more drivers, wherein the plurality of control signals control the one or more drivers to cause each of the k groups of subpixels to sequentially emit lights in a respective one of k sub-frame periods within a frame period;
• and
• a data converting module configured to convert original display data into converted display data based on a manner in which the array of subpixels is divided into the k groups of subpixels, wherein the k groups of subpixels emit lights based on the converted display data,
• wherein the control signal generating module is configured to provide a first set of control signals of the plurality of control signals to a light emitting driver of the one or more drivers to control the light emitting driver to cause each of the k groups of subpixels to sequentially emit lights in the respective sub-frame period within the frame period, and
• wherein the first set of control signals comprises one or more clock signals, k light emitting enable signals, and a light emitting control enable signal that is a logical disjunction of the k light emitting enable signals.

A system, comprising:

• a display panel comprising:
• an array of OLEDs divided into k groups of OLEDs, where k is an integer larger than 1;
• a plurality of pixel circuits connected to the array of OLEDs, wherein each of the plurality of pixel circuits is configured to drive k OLEDs from each of the k groups of OLEDs;
• a light emitting driver connected to the plurality of pixel circuits and configured to cause each of the k groups of OLEDs to sequentially emit lights in a respective one of k sub-frame periods within a frame period;
• and
• a gate scanning driver connected to the plurality of pixel circuits and configured to sequentially scan each of the k groups of OLEDs in the respective sub-frame period within the frame period, wherein:
• each of the plurality of pixel circuits comprises:
• a capacitor,
• a light emitting control transistor comprising a gate electrode connected to a light emitting control signal provided by the light emitting driver, a source electrode connected to a supply voltage signal, and a drain electrode connected to a driving transistor,
• the driving transistor comprising a gate electrode connected to one electrode of the capacitor, a source electrode connected to the drain electrode of the light emitting control transistor, and a drain electrode connected to k light emitting transistors of the k OLEDs,
• the k light emitting transistors, each of which comprising a gate electrode connected to a respective one of k light emitting signals provided by the light emitting driver, a source electrode connected to the drain electrode of the driving transistor, and a drain electrode connected to a respective one of the k OLEDs, and
• the light emitting driver comprises a light emitting circuit and a light emitting control circuit, the light emitting circuit comprises k first shift registers configured to provide k light emitting signals in response to k first enable signals, and the light emitting control circuit comprises a second shift register configured to provide the light emitting control signal in response to a second enable signal that is a logical disjunction of the k first enable signals,
• a processor configured to convert original display data into converted display data based on a manner in which the array of OLEDs is divided into the k groups of OLEDs;
• and
• a control logic connected to the processor and configured to provide a plurality of control signals based on the converted display data.