Optimizing cache energy consumption in processor-based devices

A processor-based device, comprising:

• means for receiving an effective address (EA) for a memory access request;
• means for determining that a tag portion of the EA corresponds to a tag of a way lookup table (WLUT) entry among a plurality of WLUT entries of a WLUT circuit;
• and
• means for accessing, in a set among a plurality of sets of a cache memory device corresponding to a set portion of the EA, only a predicted tag way among a plurality of tag ways of the cache memory device indicated by a predicted way indicator of the WLUT entry and only a predicted data way among a plurality of data ways of the cache memory device indicated by the predicted way indicator of the WLUT entry, wherein the predicted way indicator comprises an identifier of the predicted tag way among the plurality of tag ways and the corresponding predicted data way among the plurality of data ways;
• wherein:
• a count of the plurality of WLUT entries corresponds to a count of the plurality of sets;
• and
• the predicted way indicator comprises a number N of bits, wherein N is a base two (2) logarithm of a count of the plurality of data ways.

A method for optimizing cache energy consumption, comprising:

• receiving, by a way lookup table (WLUT) circuit of an instruction processing circuit of a processor-based device, an effective address (EA) for a memory access request;
• determining, by the WLUT circuit, that a tag portion of the EA corresponds to a tag of a WLUT entry among a plurality of WLUT entries of the WLUT circuit;
• responsive to determining that the tag portion of the EA corresponds to the tag of the WLUT entry, transmitting, by the WLUT circuit, a predicted way indicator of the WLUT entry to a cache controller of the processor-based device, wherein the predicted way indicator comprises an identifier of a predicted tag way among a plurality of tag ways of a cache memory device and a corresponding predicted data way among a plurality of data ways of the cache memory device;
• and
• accessing, by the cache controller in a set among a plurality of sets of the cache memory device corresponding to a set portion of the EA, only the predicted tag way among the plurality of tag ways of the cache memory device indicated by the predicted way indicator and only the predicted data way among the plurality of data ways of the cache memory device indicated by the predicted way indicator;
• wherein:
• a count of the plurality of WLUT entries corresponds to a count of the plurality of sets;
• and
• the predicted way indicator comprises a number N of bits, wherein N is a base two (2) logarithm of a count of the plurality of data ways.

A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed, cause a processor of a processor-based device to:

• receive an effective address (EA) for a memory access request;
• determine that a tag portion of the EA corresponds to a tag of a way lookup table (WLUT) entry among a plurality of WLUT entries of a WLUT circuit;
• and
• access, in a set among a plurality of sets of a cache memory device corresponding to a set portion of the EA, only a predicted tag way among a plurality of tag ways of the cache memory device indicated by a predicted way indicator of the WLUT entry and only a predicted data way among a plurality of data ways of the cache memory device indicated by the predicted way indicator, wherein the predicted way indicator comprises an identifier of the predicted tag way among the plurality of tag ways and the corresponding predicted data way among the plurality of data ways;
• wherein:
• a count of the plurality of WLUT entries corresponds to a count of the plurality of sets;
• and
• the predicted way indicator comprises a number N of bits, wherein N is a base two (2) logarithm of a count of the plurality of data ways.