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US 12,379,994 B2Granted
Memory address translation for data protection and recovery
AssigneeMicron Technology, Inc.
InventorDaniele Balluchi
Life of this patent
Estimating the term…
Abstract
Address translation of host commands to access host data stored in memory devices that provides a chip kill capability not only involves locating where the host data is stored, but also involves locating where parity data striped with the host data is stored. In locating where the parity data is stored, the address translation can be performed with logical (e.g., arithmetic) operations.
Claims20
A method, comprising:
- receiving a host command including:
- a first address bit indicative of a first numerical value assigned to a row segment of a first memory device configured for first data;
- and
- a second address bit indicative of a second numerical value assigned to a first channel of a number of channels and corresponding to the first memory device;
- and
- identifying a second channel of the number of channels and corresponding to a second memory device configured for second data that are striped with the first data based at least in part on comparing the first and second numerical values.
3 more elements
An apparatus, comprising:
- a number of memory devices respectively corresponding to a number of channels;
- and
- a controller coupled to the number of memory devices via the number of channels, the controller configured to:
- receive a first address bit of a host command, the first address bit indicative of a first numerical value assigned to a row segment of a first memory device configured for first data;
- receive a second address bit of the host command, the second address bit indicative of a second numerical value assigned to a first channel of the number of channels;
- compare, in response to receipt of the host command, the first and second numerical values to identify a second channel corresponding to a second memory device configured for second data striped with the first data;
- and
- access the first memory device identified based at least in part on the first and the second address bits;
- and
- access the second memory device identified based at least in part on a result of the comparison.
7 more elements
An apparatus, comprising:
- a number of memory devices respectively corresponding to a number of channels, wherein the number of memory devices comprise a number of row segments each comprising a respective set of rows of memory cells of each memory device of the number of memory devices;
- and
- a controller coupled to the number of memory devices via the number of channels, the controller configured to:
- receive a host command including:
- a first address bit indicative of a first numerical value assigned to a row segment of the number of row segments configured for host data;
- and
- a second address bit indicative of a second numerical value assigned to a base channel associated with a first memory device configured for the host data;
- and
- to access the host data and parity data striped with the host data:
- compare the first and second numerical values to determine if the second numerical value is less than a difference between a particular amount and the first numerical value;
- identify a row of memory cells of the first memory device configured for the host data based at least in part on the first and second address bits;
- and
- identify a second memory device and a row of memory cells configured for the parity data based at least in part on the comparison.
10 more elements
Dependencies are inferred from the claim text.