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US 12,379,956 B2Granted
Processor interrupt expansion feature
AssigneeIntel Corporation
InventorsGilbert Neiger, Rajesh Sankaran
Life of this patent
Estimating the term…
Abstract
An embodiment of an integrated circuit may comprise a processor with one or more cores and circuitry coupled to the one or more cores, the circuitry to control one or more interrupts based on an interrupt expansion data structure, and report information derived from the interrupt expansion data structure to a software interrupt handler. Other embodiments are disclosed and claimed.
Claims15
An integrated circuit, comprising:
- a processor to be coupled to a memory, the processor comprising one or more cores and circuitry coupled to the one or more cores, the circuitry to:
- receive a hardware interrupt comprising:
- a first vector which is to indicate a class or interrupts;
- and
- a first index which is to identify a bit location;
- and
- based on the hardware interrupt:
- access the memory, based on the first vector, to identify a first entry of one or more tables which are to comprise multiple entries which are each indexed based on a different respective vector, and which each indicate a respective one of multiple posted-interrupt data structures (PIDs) at the memory, wherein the multiple PIDs are each to comprise:
- a respective bitmap comprising bits which each correspond to a different respective one of multiple interrupt sources;
- and
- an identifier of a respective target processor of multiple processors;
- identify a first posted-interrupt data structure (PID) of the multiple PIDs based on the first entry, wherein the first PID comprises a first bitmap, and wherein the first PID identifies a first target processor;
- access a bit of the first bitmap based on the first index;
- deliver an interrupt to a software interrupt handler;
- and
- provide event information to the first target processor based on the bit of the first bitmap.
13 more elements
A method at a processor, the method comprising:
- receiving a hardware interrupt comprising:
- a first vector which indicates a class or interrupts;
- and
- a first index which identifies a bit location;
- and
- based on the hardware interrupt:
- accessing a memory coupled to the processor, based on the first vector, to identify a first entry of one or more tables comprising multiple entries which are each indexed based on a different respective vector, and which each indicate a respective one of multiple posted-interrupt data structures (PIDs) at the memory, wherein the multiple PIDs each comprise:
- a respective bitmap comprising bits which each correspond to a different respective one of multiple interrupt sources;
- and
- an identifier of a respective target processor of multiple processors;
- identifying a first posted-interrupt data structure (PID) of the multiple PIDs based on the first entry, wherein the first PID comprises a first bitmap, and wherein the first PID identifies a first target processor;
- accessing a bit of the first bitmap based on the first index;
- delivering an interrupt to a software interrupt handler;
- and
- providing event information to the first target processor based on the bit of the first bitmap.
12 more elements
An apparatus, comprising:
- memory to store:
- multiple posted-interrupt data structures (PIDs) which are each to comprise:
- a respective bitmap comprising bits which each correspond to a different respective one of multiple interrupt sources;
- and
- an identifier of a respective target processor of multiple processors;
- and
- one or more tables comprising multiple entries which are each indexed based on a different respective vector, and which each indicate a respective one of the multiple PIDs;
- and
- a processor coupled to the memory, the processor including one or more cores and circuitry coupled to the one or more cores to:
- receive a hardware interrupt comprising:
- a first vector which is to indicate a class or interrupts;
- and
- a first index which is to identify a bit location;
- and
- based on the hardware interrupt:
- access the memory, based on the first vector, to identify a first entry of the one or more tables;
- identify a first posted-interrupt data structure (PID) of the multiple PIDs based on the first entry, wherein the first PID comprises a first bitmap, and wherein the first PID identifies a first target processor;
- access a bit of the first bitmap based on the first index;
- deliver an interrupt to a software interrupt handler;
- and
- provide event information to the first target processor based on the bit of the first bitmap.
18 more elements
Dependencies are inferred from the claim text.