Stall-driven multi-processing
AssigneeRambus Inc.
InventorFrederick A. Ware
Life of this patent
Estimating the term…
Abstract
In a microprocessor having an instruction execution unit and first and second sets of process execution resources, context information for a process next-to-be-executed by the instruction execution unit is loaded into a register file, translation lookaside buffer and first-level data cache of the first set of process execution resources during a first interval. During the first interval and concurrently with the loading of context information for the process next-to-be executed, the instruction execution unit executes a current process, including accessing context information for the current process within the register file, translation lookaside buffer and first-level data cache of the second set of process execution resources.
Claims21
A microprocessor comprising:
- an instruction execution unit to execute processes having respective virtual address spaces;
- a first set of process execution resources including at least a register file and a translation lookaside buffer;
- a second set of process execution resources including at least a register file and a translation lookaside buffer;
- context-switch circuitry that (i) is dedicated to background loading of context information into the first and second sets of prosecution resources, (ii) executes no host processes having respective virtual address spaces, and (iii) loads, without invoking instruction execution within the instruction execution unit, context information for a process to-be-executed by the instruction execution unit into the register file and translation lookaside buffer of either the first set or the second set of process execution resources during a first interval in which the instruction execution unit executes a current process and accesses context information for the current process within the register file and translation lookaside buffer of the other of the first set or the second set of process execution resources.
A method of operation within a microprocessor having (i) an instruction execution unit to execute processes having respective virtual address spaces, first and second sets of process execution resources, and (iii) context-switch circuitry dedicated to background loading of context information into the first and second sets of prosecution resources and that executes no host processes having respective virtual address spaces, the method comprising:
- executing a context load operation within the context-switch circuitry, during a first interval and without invoking instruction execution within the instruction execution unit, to load context information for a process next-to-be-executed by the instruction execution unit into a register file and translation lookaside buffer of either the first set or the second set of process execution resources;
- and
- during the first interval and concurrently with the loading of the context information for the process next-to-be executed, executing a current process within the instruction execution unit, including accessing context information for the current process within the register file and translation lookaside buffer of the other of the first set or the second set of process execution resources.
A microprocessor comprising
- a first set of process execution resources including at least a register file and a translation lookaside buffer;
- a second set of process execution resources including at least a register file and a translation lookaside buffer;
- an instruction execution unit to execute processes having respective virtual address spaces, including execution of constituent instructions of a current process during a first interval, the instruction execution unit including means for accessing context information for the current process within the register file and translation lookaside buffer of either of the first set or the second set of process execution resources;
- and
- context-switch circuitry dedicated to background loading of context information into the first and second sets of prosecution resources and that executes no host processes having respective virtual address spaces, the context-switch circuitry including means for loading, during the first interval and without invoking instruction execution within the instruction execution unit, context information for a next-to-be-executed process into the register file and translation lookaside buffer of the other of the first set or the second set of process execution resources.
Dependencies are inferred from the claim text.