Methods of fabricating planar capacitors on a shared plate electrode

A method of fabricating a device structure, the method comprising:

• forming at least a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in the first dielectric in a logic region;
• depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect;
• forming an electrode structure on the first conductive interconnect by a first process comprising:
• etching a first opening in the etch stop layer;
• and
• depositing a first conductive hydrogen barrier layer and a first conductive material in the first opening;
• depositing an electrode layer on the electrode structure and on the etch stop layer;
• forming a plurality of memory devices by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode layer and etching the material layer stack, etching to form the plurality of memory devices comprises partially recessing the electrode layer to form the electrode layer having a variable thickness;
• forming a first encapsulation layer on the plurality of memory devices and on the electrode layer;
• forming a mask over the plurality of memory devices and the electrode layer;
• using the mask to etch the first encapsulation layer and the electrode layer to form a plate electrode extending beyond a sidewall of individual ones of the plurality of memory devices;
• depositing a second encapsulation layer on the first encapsulation layer;
• depositing a second dielectric on the plurality of memory devices, and on the second encapsulation layer;
• forming a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are formed on the individual ones of the plurality of memory devices by a second process comprising:
• forming a second opening in the second dielectric and in the first encapsulation layer;
• depositing a second conductive hydrogen barrier layer and a second conductive material in the second opening;
• forming a hanging trench over the second conductive interconnect;
• forming a third opening in the second dielectric and in the etch stop layer in the logic region;
• and
• depositing a third conductive material in the third opening and in the hanging trench to form a via structure on the second conductive interconnect and a metal structure on the via structure.

A method of fabricating a device structure, the method comprising:

• forming at least a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in the first dielectric in a logic region;
• depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect;
• forming an electrode structure on the first conductive interconnect by a first process comprising:
• etching a first opening in the etch stop layer;
• and
• depositing a first conductive hydrogen barrier layer and a first conductive material in the first opening;
• depositing an electrode layer on the electrode structure and on the etch stop layer;
• forming a plurality of memory devices by a second process comprising:
• depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode layer and a second conductive hydrogen barrier layer above the ferroelectric material or the paraelectric material;
• and
• etching the material layer stack, wherein etching to form the plurality of memory devices comprises partially recessing the electrode layer to form the electrode layer having a variable thickness;
• forming a dielectric spacer on sidewalls of individual ones of the plurality of memory devices;
• forming a mask and etching the electrode layer, wherein the mask covers the plurality of memory devices and wherein etching the electrode layer forms a plate electrode that extends beyond sidewalls of the plurality of memory devices;
• depositing a second dielectric on the plurality of memory devices and on the dielectric spacer;
• forming a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are formed on individual ones of the plurality of memory devices by a third process comprising:
• forming a second opening in the second dielectric;
• depositing a third conductive hydrogen barrier layer and a second conductive material in the second opening;
• forming a hanging trench over the second conductive interconnect;
• forming a third opening in the second dielectric, and in the etch stop layer in the logic region;
• and
• depositing a third conductive material in the third opening and in the hanging trench to form a via structure on the second conductive interconnect and a metal structure on the via structure.