Three level switching converter and control

A circuit comprising:

• first, second, third, and fourth transistors coupled in series;
• and
• a control circuit coupled to the first, second, third, and fourth transistor, the control circuit including a clock generator, a first current sense circuit, and a second current sense circuit, in which:
• the clock generator is configured to generate first and second clocks, in which the second clock is in quadrature with the first clock;
• the first current sense circuit is configured to sense a current flowing through the first transistor;
• the second current sense circuit is configured to sense a current flowing through the fourth transistor;
• and
• the control circuit is configured to:
• operate the first, second, third, and fourth transistors in a pulse frequency modulation (PFM) mode;
• define a pre-PFM zone based on the current flowing through the fourth transistor being zero at an edge of the second clock;
• and
• in the pre-PFM zone:
• disable turn-on of the fourth transistor;
• and
• exit the pre-PFM zone responsive to the current flowing through the fourth transistor not being zero at an edge of the second clock.

A backlight system comprising:

• a light emitting diode (LED);
• and
• a three-level switching converter coupled to the LED, the three-level switching converter including:
• first, second, third, and fourth transistors coupled in series;
• and
• a control circuit coupled to the first, second, third, and fourth transistors, the control circuit including a clock generator, a first current sense circuit, a second current sense circuit, and a zero current differentiation zone (ZC_DF) circuit, in which:
• the clock generator is configured to generate first and second clocks, in which the second clock is in quadrature with the first clock;
• the first current sense circuit is configured to sense a current flowing through the first transistor;
• the ZC_DF circuit is configured to define a ZC_DF interval starting at an edge of the second clock and ending at turn-on of the fourth transistor;
• and
• the control circuit is configured to operate the first, second, third, and fourth transistors in a discontinuous conduction mode (DCM), and, in the DCM:
• turn off the first transistor during the ZC_DF interval responsive to the current flowing through the first transistor being negative;
• and
• turn off the second transistor during the ZC_DF interval responsive to the current flowing through the fourth transistor being negative.