Physical layer transceiver with reduced variation in packet latency

A physical layer transceiver comprising:

• physical coding sublayer circuitry and physical medium attachment circuitry, the physical coding sublayer circuitry being configured for transport of data between a host device and the physical medium attachment circuitry, and the physical medium attachment circuitry being configured for transport of data between the physical coding sublayer circuitry and a channel medium;
• and
• clock and control circuitry configured to provide a clock standard to the physical coding sublayer circuitry and the physical medium attachment circuitry, the clock standard being converted to a first clock for a first clock domain of the physical coding sublayer circuitry and a second clock for a second clock domain of the physical medium attachment circuitry, the clock and control circuitry further being configured to reduce impact of variation in latency in data transport between the first clock domain and the second clock domain by:
• determining, during an initial training of a link, a transmit latency value in a transmit direction from the first clock domain to the second clock domain;
• determining, during the initial training of the link, a receive latency value in a receive direction from the second clock domain to the first clock domain;
• and
• using the transmit latency value and the receive latency value to account for latency in transfer of data between the first clock domain and the second clock domain following the initial training until a subsequent training.