Error rate measurement apparatus and error rate measurement method
AssigneeAnritsu Corporation
InventorHisao Kidokoro
Life of this patent
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AssigneeAnritsu Corporation
InventorHisao Kidokoro
Estimating the term…
An operation unit 2 sets a Flit length according to the number of lanes, a mask pattern length and a mask pattern period for masking a portion corresponding to an SKP OS, and a threshold value for Flit error determination. In an error detector 4, a symbol mask generation unit 25 generates a mask pattern, an error detection unit 28 detects and counts an error in the portion corresponding to Flit by dividing the mask pattern at intervals of a Flit length of a PAM4 signal from a device under test, and masking a portion corresponding to the SKP OS with the mask pattern, and a Flit error detection unit 29 detects and counts an FEC symbol error in the portion corresponding to Flit for each ECC group, and determines the ECC group in which the number of FEC symbol errors exceeds a threshold value to be a Flit error.
An error rate measurement apparatus comprising:
An error rate measurement method using an operation unit that performs a setting, and an error detector that receives a pulse amplitude modulation 4 (PAM4) signal based on bit string data of a pseudo random bit sequence (PRBS) pattern transmitted from a device under test and that detects an error, wherein
Dependencies are inferred from the claim text.