Feedback controlled high-speed transmitter

Differential signaling transmitter circuitry comprising:

• a first driver stack including a first bias transistor having a source/drain path coupled to a first terminal in series with the source/drain path of at least one first blocking transistor in the first driver stack;
• a second driver stack including a second bias transistor having a source/drain path coupled to a second terminal in series with the source/drain path of at least one first blocking transistor in the second driver stack;
• first replica circuitry adapted to generate a first bias reference voltage by controlling a gate voltage of a replica of the first bias transistor in a first replica stack, the first replica stack including a replica of the first bias transistor and a replica of the at least one first blocking transistor in the first driver stack;
• and
• second replica circuitry adapted to generate a second bias reference voltage by controlling a gate voltage of a replica of the second bias transistor in a second replica stack, the second replica stack including the replica of the second bias transistor and replicas of the at least one first blocking transistor in the second driver stack, the second replica stack coupled in series with a third replica stack including replicas of the first bias transistor and a replica of the at least one first blocking transistor in the first driver stack, the gate of the replica of the first bias transistor in the third replica stack receiving the gate voltage controlled by the first replica circuitry;
• first switching circuitry adapted to couple a first gate voltage corresponding to the first bias reference voltage to the gate of the first bias transistor in the first driver stack responsive to a data signal;
• and
• second switching circuitry adapted to couple a second gate voltage corresponding to the second bias reference voltage to the gate of the second bias transistor in the second driver stack responsive to the data signal.

A network node comprising:

• a microcontroller unit (MCU);
• first and second terminals, adapted to be coupled to first and second lines of a network bus;
• receiver circuitry, coupled to the first and second terminals, and configured to receive signals on the network bus for forwarding to the MCU;
• and
• transmitter circuitry, coupled to the first and second terminals, and configured to transmit signals onto the network bus responsive to data signals from the MCU, the transmitter circuitry comprising:
• an upper driver stack comprising:
• an upper bias transistor, having a source/drain path and a gate, the source/drain path coupled to a supply node;
• at least one upper blocking transistor coupled in series with the source/drain path of the upper bias transistor;
• a lower driver stack, comprising:
• a lower bias transistor, having a source/drain path and a gate;
• and
• at least one lower blocking transistor coupled in series with the source/drain path of the lower bias transistor and coupled to a common node;
• a first control loop comprising:
• a first replica stack including replicas of the bias transistor and at least one blocking transistor in a first one of the upper and lower driver stacks, coupled in series;
• a first reference leg coupled between the supply node and the common node;
• and
• a first differential amplifier having a first input coupled to the first replica stack, a second input coupled to the first reference leg, and an output coupled to a gate of the replica bias transistor in the first replica stack;
• a second control loop comprising:
• a second replica stack including replicas of the bias transistor and at least one blocking transistor in a second one of the upper and lower driver stacks, coupled in series between the supply node and the common node;
• a third replica stack including replicas of the bias transistor and at least one blocking transistor in the first one of the upper and lower driver stacks, the third replica stack coupled to the second replica stack at an output node and in series with the second replica stack between the supply node and the common node, the replica bias transistor in the third replica stack having a gate coupled to the output of the first differential amplifier;
• a second reference leg coupled between the supply node and the common node;
• and
• a second differential amplifier having a first input coupled to the output node, a second input coupled to the output node, and an output coupled to a gate of the replica bias transistor in the second replica stack;
• first switching circuitry configured to couple the output of the first differential amplifier to the gate of the bias transistor of the first one of the upper and lower driver stacks responsive to a data signal;
• and
• second switching circuitry configured to couple the output of the second differential amplifier is coupled to the gate of the bias transistor of the second one of the upper and lower driver stacks responsive to the data signal.