Clock management apparatus, clock frequency division module and system-on-chip

A clock frequency division module, comprising a state machine, a synchronization signal delay circuit, and a clock generation circuit;

• wherein the synchronization signal delay circuit is configured to delay a synchronization signal after receiving the synchronization signal;
• the state machine is configured to, after receiving the delayed synchronization signal, control the clock generation circuit to adjust a phase of the output clock in response to a current clock signal and other clock signals being in an asynchronous state;
• wherein the clock frequency division module further comprises a counter and a comparator;
• wherein the counter is configured to perform periodic counting under control of the state machine to determine a current count value;
• the comparator is configured to compare the current count value with a maximum count threshold of the clock frequency division module, and output state information about whether a current state is a synchronous state;
• the comparator is configured to output the state information that the current state is a synchronous state in response to the current count value being consistent with the maximum count threshold, and output the state information that the current state is an asynchronous state in response to the current count value being inconsistent with the maximum count threshold;
• the state machine is configured to receive the state information sent by the comparator;
• wherein the maximum count threshold is a value obtained by subtracting 1 from a preset frequency division ratio of the clock frequency division module.

A system-on-chip, comprising a clock management apparatus, wherein the clock management apparatus is configured to output clock signals for use in the same or different functional modules of the system-on-chip;

• the clock management apparatus comprising a clock synchronization signal generator, a plurality of clock gating units, and a plurality of clock frequency division modules;
• wherein the clock synchronization signal generator is configured to generate a synchronization signal of a predetermined period;
• the plurality of clock gating units are in one-to-one correspondence with the plurality of clock frequency division modules, and each of the plurality of clock gating units is connected in series with a corresponding one of the plurality of clock frequency division modules to form a signal processing branch;
• a plurality of the signal processing branches are connected in parallel and configured to receive a source clock signal respectively;
• the clock gating unit is configured to control an on-off switch of the signal processing branch, and the clock frequency division module is configured to perform phase adjustment on a clock signal of the signal processing branch after receiving a synchronization signal output by the clock synchronization signal generator, to adjust clock signals of the plurality of signal processing branches from an asynchronous state to a synchronous state.