US 12,374,657 B2Granted

Stacked integrated circuit device

AssigneeGraphcore Limited

InventorsStephen Felix, Phillip Horsfield, Simon Jonathan Stacey

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Abstract

The first logic wafer is attached to a supporting wafer, which adds sufficient depth to this bonded structure such that the first logic wafer may be thinned during the manufacturing process. The first logic wafer is thinned such that the through silicon vias may be etched in the substrate of the first logic wafer so as to provide adequate connectivity to a second logic wafer, which is bonded to the first logic wafer. The second logic wafer adds sufficient depth to this bonded structure to allow the supporting wafer to then be thinned to enable through silicon vias to be added to the supporting wafer so as to provide appropriate connectivity for the entire stacked structure. The thinned supporting wafer is retained in the finished stacked wafer structure and may comprise additional components (e.g. capacitors) supporting the operation of the processing circuitry in the logic wafers.

Claims34

Dependent claims

A method of manufacturing at least one stacked integrated circuit device, the method comprising:

providing a supporting wafer comprising a silicon substrate and a first plurality of metal layers, the first plurality of metal layers providing an inner facing surface of the supporting wafer, the silicon substrate providing an outer facing surface of the supporting wafer, the supporting wafer having a self-supporting depth;
providing a first logic wafer having a front surface, which is a surface of a second plurality of metal layers of the first logic wafer, the second plurality of metal layers comprising first processing circuitry, the first processing circuitry comprising a first set of processing units configured to execute computer readable instructions;
providing a second logic wafer having a front surface, which is a surface of a third plurality of metal layers of the second logic wafer, the third plurality of metal layers comprising second processing circuitry, the second logic wafer having a self-supporting depth, the second processing circuitry comprising a second set of processing units configured to execute computer readable instructions;
bonding the front surface of the first logic wafer to the inner facing surface of the supporting wafer such that the second plurality of metal layers form electrical connections with the first plurality of metal layers;
thinning the first logic wafer such that the first logic wafer has a depth smaller than the self-supporting depth of the supporting wafer;
after thinning the first logic wafer, forming in the first logic wafer, first backside through silicon vias extending between the second plurality of metal layers and a back surface of the first logic wafer;
bonding the front surface of the second logic wafer to a back surface of the first logic wafer;
thinning the supporting wafer such that the supporting wafer is thinner than the second logic wafer;
after thinning the supporting wafer, forming in the supporting wafer, second backside through silicon vias extending between the outer facing surface of the supporting wafer and the first plurality of metal layers;
and
providing on the outer facing surface of the supporting wafer, a plurality of connector terminals configured to connect the at least one stacked integrated circuit device to a supply voltage.

8 more elements

A stacked integrated circuit device comprising:

a first die comprising a silicon substrate, the first die having an outer facing surface on which are arranged a plurality of connector terminals and a first plurality of metal layers comprising an inner facing surface connected to the connector terminals by first backside through silicon vias passing through the silicon substrate of the first die;
a first logic die having a second plurality of metal layers comprising a front surface in alignment with the inner facing surface of the first die and connected to the first die by a first set of connectors extending between the inner facing surface of the first die and the front surface of the first logic die, wherein the first logic die further comprises a back surface connected to the second plurality of metal layers by second backside through silicon vias;
and
a second logic die having a third plurality of metal layers providing a front surface of the second logic die that is in alignment with the back surface of the first logic die and connected to the first logic die by a second set of connectors arranged extending between the back surface of the first logic die and the front surface of the second logic die;
wherein the second plurality of metal layers comprises first processing circuitry comprising a first processing unit and the third plurality of metal layers comprises second processing circuitry comprising a second processing unit, the first processing unit and second processing unit being configured to execute computer readable instructions to perform computing operations.

2 more elements

A method of manufacturing a stacked integrated circuit device from a first logic wafer, a second logic wafer, and a supporting wafer, wherein the supporting wafer has a silicon substrate and a first plurality of metal layers, the first plurality of metal layers having an inner facing surface of the supporting wafer, the silicon substrate providing an outer facing surface of the supporting wafer, the supporting wafer having a self-supporting depth, wherein the first logic wafer has a front surface, which is a surface of a second plurality of metal layers of the first logic wafer, the second plurality of metal layers having first processing circuitry, the first processing circuitry having a first processing unit configured to execute computer readable instructions, and wherein the second logic wafer has a front surface, which is a surface of a third plurality of metal layers of the second logic wafer, the third plurality of metal layers having second processing circuitry, the second logic wafer having a self-supporting depth, the second processing circuitry comprising a second processing unit configured to execute computer readable instructions, the method comprising:

bonding the front surface of the first logic wafer to the inner facing surface of the supporting wafer, including forming electrical connections between the second plurality of metal layers and the first plurality of metal layers;
thinning the first logic wafer such that the first logic wafer has a depth smaller than the self-supporting depth of the supporting wafer;
after thinning the first logic wafer, forming first backside through silicon vias extending between the second plurality of metal layers and a back surface of the first logic wafer;
bonding the front surface of the second logic wafer to a back surface of the first logic wafer;
thinning the supporting wafer such that the supporting wafer is thinner than the second logic wafer;
after thinning the supporting wafer, forming second backside through silicon vias extending between the outer facing surface of the supporting wafer and the first plurality of metal layers;
and
depositing a plurality of connector terminals on the outer facing surface of the supporting wafer.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/938,135Filed 5 Oct 2022
Priority: GB 21144408 Oct 2021
Published: US 2023/0116320 A113 Apr 2023
Granted: 29 Jul 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification26 codes

H10W 90/00
Package configurations
G01R 31/31716
Input or output aspects: testing of input or output with loop-back
G01R 31/318511
Test of Modular systems, e.g. Wafers, MCM's: wafer Test
G01R 31/318536
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: scan chain arrangements, e.g. connections, test bus, analog signals