# US 12,374,581 B2 · Method for manufacturing semiconductor stack structure with ultra thin die

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- Number: US 12,374,581 B2
- Document ID: US12374581B2
- Status: Granted
- Kind: B2
- Application number: 18/893,967
- Filed: 2024-09-24
- Published: 2025-01-09
- Granted: 2025-07-29
- Earliest claimed: 2024-09-24
- Assignees: Nexthin Technology
- Applicants: Nexthin Technology
- Inventors: Tzu-wei Chiu
- Web page: https://patentgrep.com/patent/US12374581B2

## CPC

- H10P 90/1914: {using bonding}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes manufacturing a plurality of wafers each having a substrate having an active surface and a backside, and a stop layer dividing the substrate into a first substrate part at a side of the active surface and a second substrate part at a side of the backside; on a first wafer of the plurality of wafers, removing the second substrate part and the stop layer; bonding a second wafer of the plurality of wafers on the first wafer with first substrate part of the second wafer facing a surface of the first wafer that is exposed by removing the stop layer and, on the second wafer, performing the same processes of removing the second substrate part and stop layer of the second wafer; repeating the bonding and removing the second substrate part and stop layer with one or more wafers to form a stack of wafers.

## Claims

### Claim 1

A method for manufacturing a stack structure, comprising:
manufacturing a plurality of wafers, the manufacturing of each of the plurality wafers comprising:
providing a substrate having an active surface and a backside;
implanting nitrogen ions at a first depth from the active surface;
implanting oxygen ions at a second depth from the active surface of the wafer, the first depth being greater than the second depth;
performing high temperature treatment to form a silicon nitride layer at the first depth and a silicon dioxide layer at the second depth, the silicon nitride layer and the silicon dioxide layer forming a stop layer, the stop layer dividing the substrate into a first substrate part at a side of the active surface and a second substrate part at a side of the backside;
forming a plurality of conductive structures in the first substrate part;
forming a connection layer comprising a plurality of interconnection points on the active surface, the conductive structures being connected to the connection layer and the stop layer;
performing a backside grinding and thinning process on a first wafer of the plurality of wafers, comprising:
grinding the backside to remove a portion of the second substrate part at the backside;
removing the remaining second substrate part to expose the stop layer;
removing the stop layer to expose the first substrate part;
bonding a second wafer of the plurality of wafers on the first wafer with the connection layer of the second wafer facing the first substrate part of the first wafer exposed by removing the stop layer and performing the same backside grinding and thinning process on the second wafer to remove the second substrate part and the stop layer of the second wafer;
repeating the bonding and backside grinding and thinning process with one or more wafers to form a stack of bonded and thinned wafers.

### Claim 2 (depends on 1)

The method of claim 1, wherein the removing the remaining second substrate part to expose the stop layer comprises performing a wet etching process on the remaining second substrate part.

### Claim 3 (depends on 2)

The method of claim 2, wherein the wet etching process uses a selection ratio of silicon to silicon nitride of 20-80.

### Claim 4 (depends on 1)

The method of claim 1, wherein the removing the remaining second substrate part to expose the stop layer comprises performing a chemical mechanical polishing process with a selection ratio of silicon to silicon nitride of 20-80.

### Claim 5 (depends on 1)

The method of claim 1, wherein the removing the remaining second substrate part to expose the stop layer comprises performing a plasma dry etching process with a selection ratio of silicon to silicon nitride of 20-80.

### Claim 6 (depends on 1)

The method of claim 1, wherein the removing the stop layer to expose the first substrate part comprises removing the silicon nitride layer and the silicon dioxide layer in sequence.

### Claim 7 (depends on 1)

The method of claim 1, wherein the removing the stop layer to expose the first substrate part comprises performing a chemical mechanical polishing process on the silicon nitride layer to remove the silicon nitride layer with a selection ratio of silicon nitride to silicon dioxide of 10-20.

### Claim 8 (depends on 7)

The method of claim 7, wherein the removing the stop layer to expose the first substrate part comprises performing a chemical mechanical polishing process on the silicon dioxide layer to remove silicon dioxide layer with a selection ratio of silicon dioxide to silicon of 5.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first depth is about 1-5 microns from the active surface.

### Claim 10 (depends on 1)

The method of claim 1, wherein the thickness of the silicon nitride layer and the silicon dioxide layer is about 500 nanometers.

### Claim 11 (depends on 1)

The method of claim 1, wherein the plurality of conductive structures include through silicon vias and the positions of the through silicon vias of the first wafer correspond to the interconnection points of the connection layer of the second semiconductor wafer.

### Claim 12

A method for manufacturing a semiconductor stack structure, comprising:
manufacturing a plurality of semiconductor wafers, wherein each of the plurality of semiconductor wafers is manufactured by the following steps:
providing a semiconductor substrate having an active surface and a backside; and
carrying out a nitrogen ion implantation process at a first depth from the active surface of the semiconductor substrate, carrying out an oxygen ion implantation process at a second depth of the semiconductor substrate, the second depth being less than the first depth, and then carrying out a high temperature treatment process to form a silicon nitride layer and a silicon dioxide layer, the silicon nitride layer and the silicon dioxide layer forming a stop layer, the stop layer dividing the semiconductor substrate into a first substrate part between the stop layer and the active surface and a second substrate part between the stop layer and the backside;
carrying out a backside grinding process from the backside of a first semiconductor wafer of the plurality of semiconductor wafers to remove a portion of the second substrate part of the semiconductor wafer;
carrying out a thinning process to form a thinned semiconductor wafer, the thinning process comprising: removing the remaining second substrate part to expose the stop layer and removing the stop layer to expose the first substrate part;
bonding another semiconductor wafer of the plurality of semiconductor wafers to the first semiconductor wafer with the active surface of the another semiconductor wafer facing a surface of the first semiconductor wafer exposed by removing the stop layer;
carrying out the same backside grinding process from the backside of the another semiconductor wafer to remove a portion of the second substrate part of the another semiconductor wafer, and carrying out the same thinning process to remove the remaining second substrate part to expose the stop layer and remove the stop layer to expose the first substrate part of the another semiconductor wafer; and
repeating the bonding, the backside grinding, and the thinning process on one or more semiconductor wafers of the plurality of semiconductor wafers to bond more wafers.

### Claim 13 (depends on 12)

The method of claim 12, wherein the steps for manufacturing each of the plurality of semiconductor wafers further comprise:
forming a plurality of conductive structures in the first substrate part between the active surface and the stop layer.

### Claim 14 (depends on 12)

The method of claim 12, wherein the steps for manufacturing each of the plurality of semiconductor wafers further comprise:
forming a connection layer on the active surface, wherein the connection layer includes interconnections points thereon.

### Claim 15 (depends on 12)

The method of claim 12, wherein the removing the stop layer to expose the first substrate part comprises removing the silicon nitride layer and then removing the silicon dioxide layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the removing the silicon nitride layer comprises one of chemical mechanical polishing or plasma dry etching with a selection ratio of silicon nitride to silicon dioxide of 10-20.

### Claim 17 (depends on 15)

The method of claim 15, wherein the removing the silicon dioxide layer comprises one of chemical mechanical polishing or plasma dry etching with a selection ratio of silicon dioxide to silicon of 5.

### Claim 18 (depends on 12)

The method of claim 12, wherein the removing the remaining second substrate part to expose the stop layer comprises one of chemical mechanical polishing, wet etching, or plasma dry etching.

### Claim 19 (depends on 18)

The method of claim 18, wherein the one of chemical mechanical polishing, wet etching, or plasma dry etching is performed with a selection ratio of silicon to silicon nitride is 20-80.

### Claim 20 (depends on 12)

The method of claim 12, wherein the removing the stop layer to expose the first substrate part comprises removing the silicon nitride layer by one of chemical mechanical polishing or plasma dry etching.

### Claim 21 (depends on 12)

The method of claim 12, wherein a depth between the stop layer structure and the active surface is 1 micron-5 microns.

### Claim 22 (depends on 12)

The method of claim 12, wherein the thickness of the silicon nitride layer is about 500 nanometers.

### Claim 23

A method for manufacturing a stack structure, comprising:
manufacturing a plurality of wafers, the manufacturing of each of the plurality wafers comprising:
providing a substrate having an active surface and a backside;
implanting nitrogen ions to form a first layer at a first depth from the active surface;
implanting oxygen ions at a second depth from the active surface of the wafer, the first depth being greater than the second depth;
performing a high temperature treatment to form a silicon nitride layer and a silicon dioxide layer to form a stop layer comprising the silicon nitride layer and the silicon dioxide layer, the stop layer dividing the substrate into a first substrate part at a side of the active surface and a second substrate part at a side of the backside;
on a first wafer of the plurality of wafers:
removing the second substrate part to expose the stop layer;
removing the stop layer to expose the first substrate part;
bonding a second wafer of the plurality of wafers on the first wafer with first substrate part of the second wafer facing a surface of the first wafer that is exposed by removing the stop layer and, on the second wafer, performing the same processes of removing the second substrate part to expose the stop layer and removing the stop layer of the second wafer to expose the first substrate part;
repeating the bonding and removing the second substrate part and the stop layer with one or more wafers to form a stack of bonded and thinned wafers.

### Claim 24 (depends on 23)

The method of claim 23, wherein the removing the stop layer to expose the first substrate part comprises removing the silicon nitride layer and the silicon dioxide layer in sequence.

### Claim 25 (depends on 23)

The method of claim 23, wherein the removing the second substrate part to expose the stop layer comprises:
grinding the backside to remove a portion of the second substrate part at the backside; and
removing the remaining second substrate part by one of chemical mechanical polishing, wet etching, or plasma dry etching.