Multi-state programming of memory cells
AssigneeMicron Technology, Inc.
InventorsJeremy M. Hirst, Shanky K. Jain, Hernan A. Castro, Richard K. Dodge, William A. Melton
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Abstract
The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.
Claims15
An apparatus, comprising:
- a memory having a plurality of memory cells;
- and
- circuitry configured to program a memory cell of the plurality of memory cells to one of at least three possible data states by:
- applying a first voltage pulse to the memory cell;
- determining the memory cell snaps back in response to the first voltage pulse;
- and
- applying a number of additional voltage pulses to the memory cell after determining the memory snaps back in response to the first voltage pulse;
- and
- wherein the circuitry includes:
- a sense amplifier configured to determine the memory cell snaps back in response to the first voltage pulse;
- and
- a latch coupled to the sense amplifier and configured to store a data value indicating the memory cell snapped back in response to the first voltage pulse, wherein the latch is configured to, responsive to storing the data value indicating the memory cell snapped back in response to the first voltage pulse, output a signal to turn off a current to the memory cell.
An apparatus, comprising:
- a memory having a plurality of memory cells;
- and
- circuitry configured to program a memory cell of the plurality of memory cells to one of at least three possible data states by:
- applying a first voltage pulse to the memory cell;
- determining the memory cell snaps back in response to the first voltage pulse;
- and
- applying a single additional voltage pulse to the memory cell after determining the memory snaps back in response to the first voltage pulse;
- and
- wherein the circuitry includes:
- a sense amplifier configured to determine the memory cell snaps back in response to the first voltage pulse;
- and
- a latch coupled to the sense amplifier and configured to store a data value indicating the memory cell snapped back in response to the first voltage pulse, wherein the latch is configured to, responsive to storing the data value indicating the memory cell snapped back in response to the first voltage pulse, output a signal to turn off a current to the memory cell.
A method of operating memory, comprising:
- programming a memory cell to one of at least three possible data states by:
- applying a first voltage pulse to the memory cell;
- determining the memory cell snaps back in response to the first voltage pulse;
- and
- applying one additional voltage pulse to the memory cell after determining the memory cell snaps back in response to the first voltage pulse;
- or
- applying two additional voltage pulses to the memory cell after determining the memory cell snaps back in response to the first voltage pulse, wherein each of the two additional voltage pulses have a same magnitude.
Dependencies are inferred from the claim text.