Resistive memory apparatus and operating method thereof and memory cell array thereof

An operating method of a resistive memory apparatus, wherein the resistive memory apparatus comprises a memory cell array and at least one dummy transistor, the memory cell array comprises a plurality of memory cells,

• each of the memory cells comprises a resistive switching element, and the operating method comprises:
• providing a first bit line voltage, a source line voltage and a word line voltage to the at least one dummy transistor to determine a value of a saturation current of the at least one dummy transistor, wherein the at least one dummy transistor is electrically isolated from the resistive switching element;
• determining a value of a second bit line voltage provided to the memory cells according to the value of the saturation current;
• and
• driving the memory cells according to a determined bit line voltage so that a cell current of the memory cells is greater than a target current value,
• wherein the resistive switching element in each of the memory cells comprises:
• a bottom electrode layer;
• a resistive switching layer, disposed on the bottom electrode layer, and comprising a plurality of regions with different conduction conditions arranged in a direction different from a thickness direction of the resistive switching layer;
• and
• a top electrode layer, disposed on the resistive switching layer, and configured to receive the determined bit line voltage.