Signal sampling circuit and semiconductor memory

A semiconductor memory, comprising a signal sampling circuit, wherein the signal sampling circuit comprising a signal input circuit, a clock receiving circuit, a sampling and logic circuit, and a decoding circuit,

• wherein the signal input circuit is configured to determine a to-be-processed command signal and a to-be-processed chip select signal;
• the clock receiving circuit is configured to receive an initial clock signal and perform frequency division processing on the initial clock signal to obtain a first clock signal, wherein a clock cycle of the initial clock signal is a preset clock cycle, and a clock cycle of the first clock signal is twice the length of the preset clock cycle;
• the sampling and logic circuit is configured to perform two-stage sampling processing and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a chip select clock signal, wherein the chip select clock signal comprises two pulses, and a width of each pulse is the preset clock cycle;
• and
• the decoding circuit is configured to receive the to-be-processed chip select signal and perform decoding processing and sampling processing on the to-be-processed command signal according to the to-be-processed chip select signal and the chip select clock signal to obtain a target command signal.