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US 12,374,377 B1Granted
Ferroelectric or paraelectric wide-input minority or majority gate based low power adder
AssigneeKepler Computing Inc.
InventorsAmrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni
Life of this patent
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Abstract
A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.
Claims17
An apparatus comprising:
- a 3-input majority gate to receive a first input, a second input, and a third input, wherein the first input is a first operand, wherein the second input is a second operand, and wherein the third input is a carry-in bit;
- and
- a 5-input majority gate to receive the first input, the second input, the third input, and two times an inverted output of the 3-input majority gate, wherein the 3-input majority gate and the 5-input majority gate include a non-linear polar material, and wherein the 3-input majority gate comprises:
- a first capacitor to receive the first input, the first capacitor coupled to a node;
- a second capacitor to receive the second input, the second capacitor coupled to the node;
- and
- a third capacitor to receive the third input, wherein the third capacitor is coupled to the node, wherein the first capacitor, the second capacitor, and the third capacitor include the non-linear polar material.
4 more elements
An apparatus comprising:
- a 3-input minority gate to receive a first input, a second input, and a third input, wherein the first input is a first operand, and wherein the second input is a second operand, and wherein the third input is a carry-in bit;
- a first inverter coupled to an output of the 3-input minority gate;
- and
- a 5-input minority gate to receive the first input, the second input, the third input, and two times an output of the 3-input minority gate, wherein the 3-input minority gate comprises:
- a first capacitor to receive the first input, the first capacitor coupled to a node;
- a second capacitor to receive the second input, the second capacitor coupled to the node;
- a third capacitor to receive the third input, wherein the third capacitor is coupled to the node;
- and
- a second inverter coupled to the node, wherein the first capacitor, the second capacitor, and the third capacitor include non-linear polar material.
6 more elements
A system comprising:
- a processor circuitry to execute one or more instructions;
- a communication interface communicatively coupled to the processor circuitry;
- and
- a memory coupled to the processor circuitry, wherein the processor circuitry comprises an adder circuitry which includes:
- a 3-input majority gate to receive a first input, a second input, and a third input, wherein the first input is a first operand, wherein the second input is a second operand, and wherein the third input is a carry-in bit;
- and
- a 5-input majority gate to receive the first input, the second input, the third input, and two times an inverted output of the 3-input majority gate, wherein the 3-input majority gate and the 5-input majority gate include non-linear polar material, and wherein the 3-input majority gate comprises:
- a first capacitor to receive the first input, the first capacitor coupled to a node;
- a second capacitor to receive the second input, the second capacitor coupled to the node;
- and
- a third capacitor to receive the third input, wherein the third capacitor is coupled to the node, wherein the first capacitor, the second capacitor, and the third capacitor include non-linear polar material.
8 more elements
Dependencies are inferred from the claim text.